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Renesas RA4 Efficiency Series User Manual

Renesas RA4 Efficiency Series User Manual

32-bit mcu

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RA4W1 Group

32-bit MCU

Renesas Advanced (RA) Family

Renesas RA4 - Efficiency Series

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

User's Manual: Hardware

Rev.0.50

Preliminary

Sep 2019

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Summary of Contents for Renesas RA4 Efficiency Series

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document.
Page 3 General Precautions 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs.
Page 4 Audience This manual is written for system designers who are designing and programming applications using the Renesas Microcontroller. The user is expected to have basic knowledge of electrical circuits, logic circuits, and the MCU.
Page 5 Numbering Notation The following numbering notation is used throughout this manual: Example Description 011b Binary number. For example, the binary equivalent of the number 3 is 011b. Hexadecimal number. For example, the hexadecimal equivalent of the number 31 is described 1Fh. In some cases, a hexadecimal number is shown with the prefix 0x, based on C/C++ formatting.
Page 6 Register Description Each register description includes both a register diagram that shows the bit assignments and a register bit table that describes the content of each bit. The example of symbols used in these tables are described in the sections that follow. The following is an example of a register description and associated bit field definition.
Page 7 Abbreviations Abbreviations used in this manual are shown in the following table: Abbreviation Description Advanced Encryption Standard Advanced High-Performance Bus AHB-AP AHB Access Port Advanced Peripheral Bus Alleged RC Advanced Trace Bus Binary Coded Decimal BSDL Boundary Scan Description Language Data Encryption Standard Digital Signature Algorithm Elliptic Curve Cryptography...
Page 8 All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained in this document is owned, controlled or licensed by or to Renesas, and is protected by trade dress, copyright, patent and trademark laws, and other intellectual property rights and unfair competition laws. Except as expressly provided herein,...
Page 9: Table Of Contents
Contents Features ..............................47 Overview ............................48 Function Outline........................48 Block Diagram ........................54 Part Numbering........................54 Function Comparison......................56 Pin Functions ........................57 Pin Assignments ........................60 Pin Lists ..........................61 CPU ..............................64 Overview..........................64 2.1.1 CPU ..........................64 2.1.2 Debug ...........................
Page 10 Flash Patch and Break Unit ....................75 SysTick System Timer ......................75 2.10 CoreSight Time Stamp Generator ..................75 2.11 OCD Emulator Connection ....................75 2.11.1 DBGEN......................... 76 2.11.2 Unlock ID Code ......................76 2.11.3 Restrictions on Connecting an OCD Emulator ............. 76 2.11.3.1 Starting connection while in low power mode ............
Page 11 6.3.5 Watchdog Timer Reset....................96 6.3.6 Software Reset ......................97 6.3.7 Determination of Cold/Warm Start................97 6.3.8 Determination of Reset Generation Source..............97 Option-Setting Memory ........................99 Overview..........................99 Register Descriptions......................99 7.2.1 Option Function Select Register 0 (OFS0) ..............99 7.2.2 Option Function Select Register 1 (OFS1) ..............
Page 12 9.2.5 Memory Wait Cycle Control Register (MEMWAIT) ............. 124 9.2.6 Main Clock Oscillator Control Register (MOSCCR) ........... 126 9.2.7 Sub-Clock Oscillator Control Register (SOSCCR) ............. 127 9.2.8 Low-Speed On-Chip Oscillator Control Register (LOCOCR) ........128 9.2.9 High-Speed On-Chip Oscillator Control Register (HOCOCR) ........129 9.2.10 Middle-Speed On-Chip Oscillator Control Register (MOCOCR) ........
Page 13 9.8.8 IWDT-Dedicated Clock (IWDTCLK) ................148 9.8.9 AGT-Dedicated Clock (AGTSCLK, AGTLCLK) ............149 9.8.10 SysTick Timer-Dedicated Clock (SYSTICCLK) ............149 9.8.11 Segment LCDC Source Clock (LCDSRCCLK)............149 9.8.12 Clock/Buzzer Output Clock (CLKOUT)............... 149 9.8.13 JTAG Clock (JTAGTCK)..................... 149 9.8.14 Clocks for BLE......................149 Usage Notes ........................
Page 14 11.2.10 Snooze Request Control Register (SNZREQCR) ............171 11.2.11 Flash Operation Control Register (FLSTOP).............. 173 11.2.12 Power Save Memory Control Register (PSMCR)............173 11.2.13 System Control OCD Control Register (SYOCDCR)..........174 11.3 Reducing Power Consumption by Switching Clock Signals ..........174 11.4 Module-Stop Function......................
Page 15 12.1.3 VBATT Pin Low Voltage Detection................193 12.1.4 VBATT_R Low Voltage Detection ................193 12.1.5 Backup Registers ....................... 193 12.1.6 VBATT Wakeup Control Function ................193 12.1.7 Time capture Pin Detection ..................194 12.2 Register Descriptions......................196 12.2.1 VBATT Control Register 1 (VBTCR1)................. 196 12.2.2 VBATT Control Register 2 (VBTCR2).................
Page 16 14.2.8 SYS Event Link Setting Register (SELSR0)............... 221 14.2.9 Wake Up Interrupt Enable Register (WUPEN) ............221 14.3 Vector Table ........................223 14.3.1 Interrupt Vector Table....................223 14.3.2 Event Number......................224 14.4 Interrupt Operation......................229 14.4.1 Detecting Interrupts ....................229 14.4.2 Selecting Interrupt Request Destinations ..............
Page 17 16.2 CPU Stack Pointer Monitor....................243 16.2.1 Protection of Registers ....................246 16.2.2 Overflow/Underflow Error ................... 246 16.2.3 Register Descriptions ....................246 16.2.3.1 Main Stack Pointer (MSP) Monitor Start Address Register (MSPMPUSA) ..247 16.2.3.2 Main Stack Pointer (MSP) Monitor End Address Register (MSPMPUEA) ..247 16.2.3.3 Process Stack Pointer (PSP) Monitor Start Address Register (PSPMPUSA) ..
Page 18 16.6.1.2 Security MPU Program Counter End Address Register (SECMPUPCEn) (n = 0, 1) ......................267 16.6.1.3 Security MPU Region 0 Start Address Register (SECMPUS0)......267 16.6.1.4 Security MPU Region 0 End Address Register (SECMPUE0) ......268 16.6.1.5 Security MPU Region 1 Start Address Register (SECMPUS1)......268 16.6.1.6 Security MPU Region 1 End Address Register (SECMPUE1) ......
Page 19 17.4.1 Transfer End by Completion of Specified Total Number of Transfer Operations ..298 17.4.2 Transfer End by Repeat Size End Interrupt..............298 17.4.3 Transfer End by Interrupt on Extended Repeat Area Overflow ........298 17.4.4 Precautions for the End of DMA Transfer..............299 17.5 Interrupts..........................
Page 20 18.6.3 Chain Transfer when Counter = 0 ................324 18.7 Interrupt Source ........................325 18.8 Event Link ........................... 325 18.9 Snooze Control Interface ....................325 18.10 Module-Stop Function......................325 18.11 Usage Notes ........................326 18.11.1 Transfer Information Start Address ................326 Event Link Controller (ELC) ......................
Page 21 20.5.3 Port Output Data Register (PODR) Summary ............346 20.5.4 Notes on Using Analog Functions ................346 20.5.5 I/O Buffer Specification....................346 20.5.6 Selecting the USB_DP and USB_DM Pins ..............346 20.5.7 Pull-up/Pull-down Setting for P914 and P915 using USBFS/GPIO Function ..... 347 20.6 Peripheral Select Settings for each Product ...............
Page 22 23.2.7 General PWM Timer Clear Source Select Register (GTCSR) ........379 23.2.8 General PWM Timer Up Count Source Select Register (GTUPSR) ......381 23.2.9 General PWM Timer Down Count Source Select Register (GTDNSR)...... 384 23.2.10 General PWM Timer Input Capture Source Select Register A(GTICASR) ....386 23.2.11 General PWM Timer Input Capture Source Select Register B(GTICBSR) ....
Page 23 23.3.8.2 Synchronized operation by hardware..............456 23.3.9 PWM Output Operation Examples ................458 23.3.10 Phase Counting Function ................... 464 23.3.11 Output Phase Switching (GPT_OPS)................. 471 23.3.11.1 Input selection and synchronization of external input signal ......474 23.3.11.2 Input sampling ....................475 23.3.11.3 Input phase decode....................
Page 24 24.2.8 AGT Event Pin Select Register (AGTISR)..............496 24.2.9 AGT Compare Match Function Select Register (AGTCMSR) ........497 24.2.10 AGT Pin Select Register (AGTIOSEL) ............... 497 24.3 Operation ..........................498 24.3.1 Reload Register and Counter Rewrite Operation ............498 24.3.2 Reload Register and Compare Register A/B Rewrite Operation........
Page 25 25.2.11 Hour Alarm Register (RHRAR)/Binary Counter 2 Alarm Register (BCNT2AR) ........................ 520 25.2.12 Day-of-Week Alarm Register (RWKAR)/Binary Counter 3 Alarm Register (BCNT3AR) ........................ 521 25.2.13 Date Alarm Register (RDAYAR)/Binary Counter 0 Alarm Enable Register (BCNT0AER) ......................522 25.2.14 Month Alarm Register (RMONAR)/Binary Counter 1 Alarm Enable Register (BCNT1AER) ......................
Page 26 25.6.2 Use of Periodic Interrupts ................... 547 25.6.3 RTCOUT (1-Hz/64-Hz) Clock Output ................. 548 25.6.4 Transitions to Low Power Modes after Setting Registers........... 548 25.6.5 Notes on Writing to and Reading from Registers ............548 25.6.6 Changing the Count Mode..................548 25.6.7 Initialization Procedure when the RTC is not to be Used ...........
Page 27 27.3.5 Interrupt Sources ......................571 27.3.6 Reading the Down-counter Value................571 27.4 Link Operation by ELC......................571 27.5 Usage Notes ........................572 27.5.1 Refresh Operations ....................572 27.5.2 Clock Division Ratio Setting ..................572 USB 2.0 Full-Speed Module (USBFS) ..................573 28.1 Overview..........................
Page 28 28.2.29 Pipe Cycle Control Register (PIPEPERI) ..............609 28.2.30 PIPEn Control Registers (PIPEnCTR) (n = 1 to 9) ............. 610 28.2.31 PIPEn Transaction Counter Enable Register (PIPEnTRE) (n = 1 to 5) ...... 616 28.2.32 PIPEn Transaction Counter Register (PIPEnTRN) (n = 1 to 5) ........617 28.2.33 Device Address n Configuration Register (DEVADDn) (n = 0 to 5)......
Page 29 28.3.4.10 OUT-NAK mode ....................642 28.3.4.11 Null auto response mode ................... 643 28.3.5 FIFO Buffer Memory....................643 28.3.6 FIFO Buffer Clearing ....................643 28.3.7 FIFO Port Functions ....................644 28.3.8 DMA Transfers (D0FIFO and D1FIFO Ports) ............. 645 28.3.9 Control Transfers Using DCP ..................645 28.3.9.1 Control transfers in host controller mode ............
Page 30 29.2.10 Serial Mode Register for Smart Card Interface Mode (SMR_SMCI) (SCMR.SMIF = 1) ...................... 672 29.2.11 Serial Control Register (SCR) for Non-Smart Card Interface Mode (SCMR.SMIF = 0) ...................... 673 29.2.12 Serial Control Register for Smart Card Interface Mode (SCR_SMCI) (SCMR.SMIF = 1) .......................
Page 31 29.5.2 CTS and RTS Functions..................... 738 29.5.3 SCI Initialization in Clock Synchronous Mode ............739 29.5.4 Serial Data Transmission in Clock Synchronous Mode..........741 29.5.5 Serial Data Reception in Clock Synchronous Mode........... 745 29.5.6 Simultaneous Serial Data Transmission and Reception in Clock Synchronous Mode...................
Page 32 29.14.3 Break Detection and Processing ................786 29.14.4 Mark State and Production of Breaks................. 787 29.14.5 Receive Error Flags and Transmit Operations in Clock Synchronous and Simple SPI Modes ...................... 787 29.14.6 Restrictions on Clock Synchronous Transmission in Clock Synchronous and Simple SPI Modes ......................
Page 33 30.7 Address Match Detection....................835 30.7.1 Slave-Address Match Detection ................. 835 30.7.2 Detection of General Call Address ................837 30.7.3 Device ID Address Detection..................838 30.7.4 Host Address Detection....................839 30.8 Wakeup Function........................ 840 30.8.1 Normal Wakeup Mode 1..................... 841 30.8.2 Normal Wakeup Mode 2.....................
Page 34 31.2.1 Control Register (CTLR)..................... 868 31.2.2 Bit Configuration Register (BCR)................871 31.2.3 Mask Register k (MKRk) (k = 0 to 7) ................873 31.2.4 FIFO Received ID Compare Registers 0 and 1 (FIDCR0 and FIDCR1) ....873 31.2.5 Mask Invalid Register (MKIVLR) ................875 31.2.6 Mailbox Register j (MBj_ID, MBj_DL, MBj_Dm, MBj_TS) (j = 0 to 31, m = 0 to 7) ..
Page 35 31.8 Interrupt ..........................912 31.9 Usage Notes ........................913 31.9.1 Settings for the Module-Stop State................913 31.9.2 Settings for the Operating Clock................. 913 Serial Peripheral Interface (SPI) ....................914 32.1 Overview..........................914 32.2 Register Descriptions......................917 32.2.1 SPI Control Register (SPCR) ..................917 32.2.2 SPI Slave Select Polarity Register (SSLP)..............
Page 36 32.3.6.2 Transmit-only operations (SPCR.TXMD = 1) ............. 955 32.3.7 Transmit Buffer Empty and Receive Buffer Full Interrupts ......... 955 32.3.8 Error Detection ......................957 32.3.8.1 Overrun errors ....................958 32.3.8.2 Parity errors......................960 32.3.8.3 Mode fault errors ....................961 32.3.8.4 Underrun errors ....................
Page 37 33.3.2 CRC Snoop ........................ 997 33.4 Usage Notes ........................998 33.4.1 Settings for the Module-Stop State................998 33.4.2 Notes on Transmission....................998 14-Bit A/D Converter (ADC14)...................... 999 34.1 Overview..........................999 34.2 Register Descriptions......................1002 34.2.1 A/D Data Registers y (ADDRy), A/D Data Duplexing Register (ADDBLDR), A/D Data Duplexing Register A (ADDBLDRA), A/D Data Duplexing Register B (ADDBLDRB), A/D Temperature Sensor Data Register (ADTSDR), A/D Internal Reference Voltage Data Register (ADOCDR) ........
Page 38 34.2.27 A/D Compare Function Window A Extended Input Channel Status Register (ADCMPSER)......................1033 34.2.28 A/D Compare Function Window B Channel Select Register (ADCMPBNSR)..1034 34.2.29 A/D Compare Function Window B Status Register (ADCMPBSR)......1036 34.2.30 A/D Compare Function Window A/B Status Monitor Register (ADWINMON) ..1036 34.2.31 A/D High-Potential/Low-Potential Reference Voltage Control Register (ADHVREFCNT).......................
Page 39 34.8.2 Notes on Stopping A/D Conversion................1067 34.8.3 A/D Conversion Restarting Timing and Termination Timing ........1068 34.8.4 Restrictions on Scan End Interrupt Handling............1068 34.8.5 Settings for the Module-Stop State................1068 34.8.6 Restrictions on Entering Low Power States ............. 1069 34.8.7 Error in Absolute Accuracy when Disconnection Detection Assistance is in Use ..
Page 40 Operational Amplifier (OPAMP) ....................1082 37.1 Overview........................... 1082 37.2 Register Descriptions......................1083 37.2.1 Operational Amplifier Mode Control Register (AMPMC) .......... 1083 37.2.2 Operational Amplifier Trigger Mode Control Register (AMPTRM)......1084 37.2.3 Operational Amplifier Activation Trigger Select Register (AMPTRS) ....... 1085 37.2.4 Operational Amplifier Control Register (AMPC) ............
Page 41 39.4.4 When Not Using the D/A Converter................1108 Capacitive Touch Sensing Unit (CTSU) ..................1109 40.1 Overview........................... 1109 40.2 Register Descriptions......................1111 40.2.1 CTSU Control Register 0 (CTSUCR0) ..............1111 40.2.2 CTSU Control Register 1 (CTSUCR1) ..............1112 40.2.3 CTSU Synchronous Noise Reduction Setting Register (CTSUSDPRS) ....1114 40.2.4 CTSU Sensor Stabilization Wait Control Register (CTSUSST) ........
Page 42 40.4.1 Measurement Result Data (CTSUSC and CTSURC Counters) ....... 1141 40.4.2 Constraints on Software Trigger................1141 40.4.3 Constraints on External Trigger................1142 40.4.4 Constraints on Forced Stops ..................1142 40.4.5 TSCAP Pin ....................... 1142 40.4.6 Constraints on Measurement Operation (CTSUCR0.CTSUSTRT Bit = 1)....1142 Data Operation Circuit (DOC) .....................
Page 43 42.4.1 Instruction Fetch from SRAM area ................1158 42.4.2 Store Buffer of SRAM ....................1158 Flash Memory ..........................1159 43.1 Overview........................... 1159 43.2 Memory Structure ......................1160 43.3 Flash Cache........................1161 43.3.1 Overview........................1161 43.3.2 Register Descriptions ....................1162 43.3.2.1 Flash Cache Enable Register (FCACHEE) ............
Page 44 43.14.8 Abnormal Termination during Programming and Erasure ........1172 43.14.9 Actions Prohibited during Programming and Erasure ..........1172 Segment LCD Controller (SLCDC) ..................... 1173 44.1 Overview........................... 1173 44.2 Register Descriptions......................1174 44.2.1 LCD Mode Register 0 (LCDM0) ................1174 44.2.2 LCD Mode Register 1 (LCDM1) ................
Page 45 48.2 DC Characteristics......................1205 48.2.1 Tj/Ta Definition ......................1205 48.2.2 I/O VIH, V IL ............................. 1205 48.2.3 I/O I OL .............................. 1207 48.2.4 I/O V , and Other Characteristics ..............1208 48.2.5 I/O Pin Output Characteristics of Low Drive Capacity ..........1209 48.2.6 I/O Pin Output Characteristics of Middle Drive Capacity ..........
Page 46 48.17.1 Transmission Characteristics ................... 1279 48.17.2 Reception Characteristics (2 Mbps) ................. 1280 48.17.3 Reception Characteristics (1 Mbps) ................. 1280 48.17.4 Reception Characteristics (500 kbps)............... 1281 48.17.5 Reception Characteristics (125 kbps)............... 1281 Appendix 1. Port States in each Processing Mode................1282 Appendix 2.
Page 47: Features
Preliminary Specifications in this document are tentative and subject to change RA4W1 Group User’s Manual ® ® High efficiency 48-MHz Arm Cortex -M4 core, 512-KB code flash memory, 96-KB SRAM, Segment LCD Controller, Capacitive Touch Sensing Unit, Bluetooth Low Energy, USB 2.0 Full-Speed, 14-Bit A/D Converter, 12-Bit D/A Converter, security and safety features.
Page 48: Overview
The MCU integrates multiple series of software- and pin-compatible Arm -based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. ® The MCU in this series incorporates a low-power and high-performance Arm Cortex...
Page 49 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 1. Overview Table 1.3 System (1 of 2) Feature Functional description Operating modes Two operating modes:  Single-chip mode  SCI/USB boot mode. section 3, Operating Modes.
Page 50 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 1. Overview Table 1.3 System (2 of 2) Feature Functional description Memory Protection Unit (MPU) Four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided for memory protection.
Page 51 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 1. Overview Table 1.6 Timers Feature Functional description General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with 4 channels and a 16-bit timer with 3 channels.
Page 52 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 1. Overview Table 1.7 Communication interfaces (2 of 2) Feature Functional description  On-chip RF transceiver and link layer compliant with the Bluetooth 5.0 Low Energy Bluetooth low energy(BLE) specification ...
Page 53 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 1. Overview Table 1.10 Data processing Feature Functional description Cyclic Redundancy Check (CRC) The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the calculator data.
Page 54: Block Diagram
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 1. Overview Block Diagram Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group may have a subset of the features.
Page 55 Code flash memory size D: 512 KB Feature set A: Security Group name W1: Wireless Communication 1 Series name 4: Up to 100MHz Renesas RA family Flash memory Renesas microcontroller Renesas Figure 1.2 Part numbering scheme Table 1.12 Product list...
Page 56: Function Comparison
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 1. Overview Function Comparison Table 1.13 Function comparison Part numbers R7FA4W1AD2CNG Pin count Package Code flash memory 512 KB Data flash memory 8 KB SRAM 96 KB 80 KB...
Page 57: Pin Functions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 1. Overview Pin Functions Function Signal Description Power supply Input Power supply pin. Connect it to the system power supply. Connect this pin to VSS by a 0.1-μF capacitor.
Page 58 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 1. Overview Function Signal Description RTCOUT Output Output pin for 1-Hz/64-Hz clock RTCIC0, RTCIC2 Input Time capture event input pins SCK0,SCK1,SCK4, Input/output pins for the clock (clock synchronous mode) SCK9 RXD0, RXD1, RXD4, Input...
Page 59 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 1. Overview Function Signal Description Comparator output VCOUT Output Comparator output pin ACMPLP CMPREF0, Input Reference voltage input pins CMPREF1 CMPIN0, CMPIN1 Input Analog voltage input pins OPAMP AMP2+...
Page 60: Pin Assignments
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 1. Overview Pin Assignments Figure 1.3 shows the pin assignments. DCLIN_D VSS_RF P402 P100 DCLIN_A P101 P404 P102 VBATT P103 P104 P215/XCIN P105 R7FA4W1AD2CNG P214/XCOUT P106...
Page 61: Pin Lists
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 1. Overview Pin Lists Pin number Timers Communication interfaces Analogs P407 AGTIO0 RTCOUT USB_VBUS CTS4_RTS4 SDA0 SSLB3 ADTRG0 SEG11 /SS4 VSS_USB P915 USB_DM P914 USB_DP VCC_USB...
Page 62 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 1. Overview Pin number Timers Communication interfaces Analogs KR00/ P100 AGTIO0 GTETRGA GTIOC5B RXD0/ SCL1 MISOA CMPIN0 IRQ2 MISO0/ SCL0/ SCK1 VSS_RF IRQ11 P501 AGTOB0 GTIV...
Page 63 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 1. Overview Pin number Timers Communication interfaces Analogs XCIN P215 XCOUT P214 XTAL IRQ2 P213 GTETRGA GTIOC0A TXD1/ MOSI1/ SDA1 EXTAL IRQ3 P212 AGTEE1 GTETRGB GTIOC0B RXD1/...
Page 64: Cpu
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 2. CPU ® ® The MCU is based on the Arm Cortex -M4 core. Overview 2.1.1  Arm Cortex-M4  Revision: r0p1-01rel0  Armv7E-M architecture profile ...
Page 65: Operating Frequency
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 2. CPU  CoreSight Trace Memory Controller with ETB configuration  Buffer size: 1 KB. reference 1. for details. 2.1.3 Operating Frequency The operating frequencies for the MCU are as follows: ...
Page 66: Mcu Implementation Options
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 2. CPU MCU Implementation Options Table 2.1 shows the implementation options of the MCU and is based on the configurable options in reference 2. Table 2.1 Implementation options Option...
Page 67: Jtag/Swd Interface
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 2. CPU JTAG/SWD Interface Table 2.3 shows the JTAG/SWD pins. Table 2.3 JTAG/SWD pins Name Width Function When not in use TCK/SWCLK Input Pos.
Page 68: Programmers Model
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 2. CPU Table 2.5 Reset or interrupt and mode setting (2 of 2) Control in On-Chip Debug (OCD) mode Reset or Interrupt name OCD break mode OCD run mode Watchdog timer reset/interrupt...
Page 69: Coresight Rom Table
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 2. CPU Table 2.6 Cortex-M4 peripheral address map Component name Start address End address Note E000 0000h E000 0FFFh reference 2. E000 1000h E000 1FFFh reference 2.
Page 70: Dbgreg Module
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 2. CPU Table 2.8 CoreSight component registers in the CoreSight ROM Table (2 of 2) Name Address Access size Initial value PID7 E00F FFDCh 32 bits 0000 0000h PID0...
Page 71: Debug Stop Control Register (Dbgstopcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 2. CPU 2.6.4.2 Debug Stop Control Register (DBGSTOPCR) Address(es): DBG.DBGSTOPCR 4001 B010h DBGSTOP_LVD DBGSTO DBGSTO — — — — — — — — —...
Page 72: Dbgreg Coresight Component Registers
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 2. CPU 2.6.4.4 DBGREG CoreSight component registers The DBGREG module provides the CoreSight component registers defined in the Arm CoreSight architecture. Table 2.10 shows these registers.
Page 73: Mcu Status Register (Mcustat)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 2. CPU IAUTH1: AID 63-32 bits Value after reset: IAUTH2 8000 0200h Address(es): IAUTH2: AID 95-64 bits Value after reset: IAUTH3 8000 0300h Address(es): IAUTH3: AID 127-96 bits Value after reset:...
Page 74: Mcu Control Register (Mcuctrl)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 2. CPU 2.6.5.3 MCU Control Register (MCUCTRL) Address(es): MCUCTRL 8000 0410h — — — — — — — — — — — — —...
Page 75: Coresight Atb Funnel
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 2. CPU CoreSight ATB Funnel There is one CoreSight ATB funnel in the MCU. The funnel has two ATB slaves and one ATB master, and it selects the debug trace source from ETM and ITM to ETB.
Page 76: Dbgen
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 2. CPU Emulator host PC To: CPU bus To: CPU debug SWJ-DP AHB-AP emulator JTAG/SWD APB-AP OCDREG comparator Option-setting memory IAUTH output Unlock ID Compare result (debug enable) Figure 2.4...
Page 77: Modifying The Unlock Id Code In Osis
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 2. CPU Table 2.14 Restrictions by mode (2 of 2) Start OCD emulator Change low power Access AHB-AP and Access APB-AP and Active mode connection mode system bus...
Page 78: References
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 2. CPU connection sequence is the same as when OSIS[127:126] is 10b except for ALeRASE capability. When IATUH0-3 are ALeRASE in ASCII code, the content of code flash, data flash, and the configuration area are erased at once.
Page 79: Operating Modes
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 3. Operating Modes Operating Modes Overview Table 3.1 shows the selection of operating modes by the mode-setting pin. For details, see section 3.2, Details of Operating Modes.
Page 80: Address Space
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 4. Address Space Address Space Overview The MCU supports a 4-GB linear address space ranging from 0000 0000h to FFFF FFFFh that can contain both program and data.
Page 81: Memory Mirror Function (Mmf)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 5. Memory Mirror Function (MMF) Memory Mirror Function (MMF) Overview The MCU provides a Memory Mirror Function (MMF). You can configure the MMF to map an application image load address in the code flash memory to the application image link address in the unused 23-bit memory mirror space addresses.
Page 82: Memmirror Enable Register (Mmen)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 5. Memory Mirror Function (MMF) 5.2.2 MemMirror Enable Register (MMEN) Address(es): MMF.MMEN 4000 1004h KEY[7:0] — — — — — — — — Value after reset: —...
Page 83 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 5. Memory Mirror Function (MMF) b24 b23 Address bus Memory mirror space [0200 0000h to 027F FFFFh] MemMirror SFR MEMMIRADDR[15:0] — — — —...
Page 84 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 5. Memory Mirror Function (MMF) ® Figure 5.3 shows the addresses handled by each module. The Arm MPU uses the original address of the CPU. The Security MPU and code flash memory each use an address after conversion through the Memory Mirror Function.
Page 85 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 5. Memory Mirror Function (MMF) Start Set MMSFR.MEMMIRADDR [15:0] (start address of the application in code flash area) Set MMEN.EN = 1 Figure 5.5 MMF setup flow R01UH0883EU0050 Rev.0.50 Page 85 of 1317...
Page 86: Setting Example
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 5. Memory Mirror Function (MMF) 5.3.2 Setting Example The target application code on the code flash can be accessed from the address of 0200 0000h on the memory mirror space by setting up the code flash start address in MMSFR.MEMMIRADDR and setting MMEN.EN to 1.
Page 87: Resets
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 6. Resets Resets Overview The MCU provides 14 resets:  RES pin reset  Power-on reset  VBATT-selected voltage power-on reset  Independent watchdog timer reset ...
Page 88 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 6. Resets Table 6.2 Reset detect flags initialized by each reset source (2 of 2) Reset source Voltage Independent Voltage RES pin Power-on monitor 0 watchdog Watchdog...
Page 89 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 6. Resets Table 6.3 Module-related registers initialized by each reset source (2 of 2) Reset source Independent Voltage watchdog Watchdog Voltage RES pin Power-on monitor 0 timer...
Page 90: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 6. Resets Table 6.4 Table 6.5 show the states of SOSC and LOCO when a reset occurs. Table 6.4 States of SOSC when a reset occurs Reset source VBATT_POR Other...
Page 91: Reset Status Register 1 (Rstsr1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 6. Resets PORF flag (Power-On Reset Detect Flag) The PORF flag indicates that a power-on reset occurred. [Setting condition]  When a power-on reset occurs. [Clearing conditions] ...
Page 92 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 6. Resets Symbol Bit name Description BUSMRF Bus Master MPU Error Reset Detect Flag 0: Bus master MPU error reset not detected R(/W) 1: Bus master MPU error reset detected.
Page 93: Reset Status Register 2 (Rstsr2)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 6. Resets [Clearing conditions]  When a reset listed in Table 6.2 occurs  When 1 is read from and then 0 is written to REERF. BUSSRF flag (Bus Slave MPU Error Reset Detect...
Page 94: Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 6. Resets CWSF flag (Cold/Warm Start Determination Flag) The CWSF flag indicates the type of reset processing, either cold start or warm start. The CWSF flag is initialized by a power-on reset.
Page 95: Voltage Monitor Reset
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 6. Resets Vdet0* VCCmin. VPOR Power-on reset state Voltage monitor 0 reset state Voltage monitor 0 reset state RES pin POR Monitor (active-low) Set by OFS1.LVDAS LVD0 enable/disable signal (active-low)
Page 96: Independent Watchdog Timer Reset
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 6. Resets Detection level Vdet1 can be changed in the Voltage Detection Level Select Register (LVDLVLR). Figure 6.2 shows example of operations during voltage monitor 1 reset. For details on the voltage monitor 1 reset, see section 8, Low Voltage Detection (LVD).
Page 97: Software Reset
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 6. Resets 6.3.6 Software Reset The software reset is an internal reset generated by a software setting of the SYSRESETREQ bit in the AIRCR register in the Arm core.
Page 98 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 6. Resets Reset exception handling RSTSR1 00h RSTSR0.LVD1RF = 1 RSTSR0. LVD0RF = 1 RSTSR0. PORF = 1 Reset corresponding to Voltage Power-on RES pin reset each bit of RSTSR1 or monitor 0...
Page 99: Option-Setting Memory
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 7. Option-Setting Memory Option-Setting Memory Overview The option-setting memory determines the state of the MCU after a reset. The option-setting memory is allocated to the configuration setting area and the program flash area of the flash memory, and the available methods of setting are different for the two areas.
Page 100 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 7. Option-Setting Memory Symbol Bit name Description b7 to b4 IWDTCKS[3:0] IWDT-Dedicated Clock 0 0 0 0: × 1 Frequency Division Ratio 0 0 1 0: × 1/16 Select 0 0 1 1: ×...
Page 101 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 7. Option-Setting Memory Note 1. The value in a blank product is FFFF FFFFh. It is set to the value written by your application. IWDTSTRT (IWDT Start Mode Select)
Page 102: Option Function Select Register 1 (Ofs1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 7. Option-Setting Memory For details, see section 26, Watchdog Timer (WDT). WDTCKS[3:0] bits (WDT Clock Frequency Division Ratio Select) The WDTCKS[3:0] bits specify the division ratio of the prescaler to divide the frequency of PCLKB as 1/4, 1/64, 1/128, 1/512, 1/2048, or 1/8192.
Page 103: Mpu Registers
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 7. Option-Setting Memory Symbol Bit name Description b5 to b3 VDSEL1[2:0] Voltage Detection 0 Level 0 0 0: Settings prohibited Select 0 0 1: Selects 2.82 V 0 1 0: Selects 2.51 V 0 1 1: Selects 1.90 V Other settings are prohibited.
Page 104: Access Window Setting Control Register (Awsc)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 7. Option-Setting Memory Table 7.1 MPU registers (2 of 2) Size Register name Symbol Function Address (byte) Security MPU Program Counter Start SECMPU Specifies the security fetch region of flash or 0000 0410h Address Register 1...
Page 105: Access Window Setting Register (Aws)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 7. Option-Setting Memory Symbol Bit name Description FSPR Protection of Access Window This bit controls the programming of the write/erase protection for and Startup Area Select the access window, the Startup Area Select Flag (BTFLG), and Function the temporary boot swap control.
Page 106: Ocd/Serial Programmer Id Setting Register (Osis)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 7. Option-Setting Memory Address Protected area Block 7 (FAWE[11:0] = 007h) Block 6 Access Non-protected Block 5 area window Block 4 (FAWS[11:0] = 004h) Block 3 Block 2 Protected...
Page 107: Setting Option-Setting Memory
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 7. Option-Setting Memory Table 7.2 Specifications for ID code protection Operating mode on boot Operations on connection to programmer or ID code State of protection on-chip debugger Serial programming mode FFh, …, FFh...
Page 108: Usage Note
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 7. Option-Setting Memory Usage Note 7.4.1 Data for Programming Reserved Areas and Reserved Bits in the Option-Setting Memory When reserved areas and reserved bits in the option-setting memory are within the scope of programming, write 1 to all bits of reserved areas and all reserved bits.
Page 109: Low Voltage Detection (Lvd)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 8. Low Voltage Detection (LVD) Low Voltage Detection (LVD) Overview The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin, and the detection level can be selected using a software program.
Page 110 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 8. Low Voltage Detection (LVD) OFS1.LVDAS Voltage detection 0 reset signal Level selection  Vdet0 Internal reference voltage circuit (for detecting Vdet0) OFS1.VDSEL1[2:0] LVCMPCR.LVD1E LVD1CR0.CMPE Voltage detection 1 signal...
Page 111: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 8. Low Voltage Detection (LVD) Register Descriptions 8.2.1 Voltage Monitor 1 Circuit Control Register 1 (LVD1CR1) Address(es): SYSTEM.LVD1CR1 4001 E0E0h IRQSE — — —...
Page 112: Voltage Monitor Circuit Control Register (Lvcmpcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 8. Low Voltage Detection (LVD) 8.2.3 Voltage Monitor Circuit Control Register (LVCMPCR) Address(es): SYSTEM.LVCMPCR 4001 E417h — — LVD1E — — — — —...
Page 113: Voltage Monitor 1 Circuit Control Register 0 (Lvd1Cr0)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 8. Low Voltage Detection (LVD) 8.2.5 Voltage Monitor 1 Circuit Control Register 0 (LVD1CR0) Address(es): SYSTEM.LVD1CR0 4001 E41Ah — — — CMPE — Value after reset: Symbol Bit name...
Page 114: Reset From Voltage Monitor 0
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 8. Low Voltage Detection (LVD) Table 8.2 Procedures to set up monitoring against Vdet1 (2 of 2) Step Monitoring the results of comparison from voltage monitor 1 Enabling output Set LVD1CR0.CMPE = 1 to enable output of the comparison results from voltage monitor 1.
Page 115 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 8. Low Voltage Detection (LVD) (1) Setting in Software Standby mode  When VCC > Vdet1 is detected, negate the voltage monitor 1 reset signal (LVD1CR0.RN = 0) following a stabilization time.
Page 116: Event Link Output
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 8. Low Voltage Detection (LVD) Figure 8.4 shows an example of the voltage monitor 1 interrupt operation. Vdet1 Lower limit on VCC voltage (VCCmin)* LVD1SR.MON Set to 0 by software LVD1SR.DET bit...
Page 117: Clock Generation Circuit
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit Clock Generation Circuit Overview The MCU provides a clock generation circuit. Table 9.1 Table 9.2 list the clock generation circuit specifications. Figure 9.1 shows a block diagram, and Table 9.3...
Page 118 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit Table 9.2 Clock Generation Circuit Specifications for the internal clocks Parameter Clock source Clock supply Specification System clock (ICLK) MOSC/SOSC/HOCO/MOCO/ CPU, DTC, DMAC, Flash, Up to 48 MHz...
Page 119 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit Note: Restrictions on setting the clock frequency: ICLK ≥ PCLKA ≥ PCLKB, PCLKD ≥ PCLKA ≥ PCLKB, ICLK ≥ FCLK Restrictions on the clock frequency ratio: (N: integer, and up to 64) ICLK:FCLK = N:1, ICLK:PCLKA = N: 1, ICLK:PCLKB = N: 1 ICLK:PCLKC = N:1 or 1:N, ICLK:PCLKD = N:1 or 1:N...
Page 120: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit Table 9.3 lists the input and output pins of the clock generation circuit. Table 9.3 Clock generation circuit input/output pins Pin name Description XTAL...
Page 121 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit Symbol Bit name Description b10 to b8 PCKB[2:0] Peripheral Module Clock B 0 0 0: ×1/1 (PCLKB) Select* 0 0 1: ×1/2 0 1 0: ×1/4 0 1 1: ×1/8 1 0 0: ×1/16...
Page 122: System Clock Source Control Register (Sckscr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit PCKB[2:0] bits (Peripheral Module Clock B (PCLKB) Select* The PCKB[2:0] bits select the frequency of peripheral module clock B (PCLKB). PCKA[2:0] bits (Peripheral Module Clock A (PCLKA) Select*...
Page 123: Pll Clock Control Register 2 (Pllccr2)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit 9.2.3 PLL Clock Control Register 2 (PLLCCR2) Address(es): SYSTEM.PLLCCR2 4001 E02Bh PLODIV[1:0] — PLLMUL[4:0] Value after reset: Symbol Bit name Description b4 to b0 PLLMUL[4:0]...
Page 124: Memory Wait Cycle Control Register (Memwait)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit PLLSTP (PLL Stop Control) The PLLSTP bit starts or stops the PLL circuit. After setting the PLLSTP bit to 0, confirm that the OSCSF.PLLSF bit is set to 1 before using the PLL clock. A fixed stabilization wait is required after setting the PLL to start operation.
Page 125 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit Setting MEMWAIT to 0 is prohibited while ICLK is faster than 32 MHz. Setting MEMWAIT to 1 is prohibited in operation modes other than High-speed mode.
Page 126: Main Clock Oscillator Control Register (Mosccr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit ICLK > 32 MHz, MEMWAIT = 1, Start FCACHEEN = 1, High-speed mode FCACHEEN bit to 0 Set ICLK  32 MHz Clear MEMWAIT bit to 0 Change the operation mode from...
Page 127: Sub-Clock Oscillator Control Register (Sosccr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit MOSCCR.MOSTP bit setting is modified for the main clock to run, only use the main clock after confirming that the OSCSF.MOSCSF bit is set to 1.
Page 128: Low-Speed On-Chip Oscillator Control Register (Lococr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit  Confirm that the sub-clock oscillator is stable when setting the sub-clock oscillator to stop.  Regardless of whether the sub-clock oscillator is selected as the system clock, ensure that oscillation by the sub- clock oscillator is stable before executing a WFI instruction to place the MCU in Software Standby mode ...
Page 129: High-Speed On-Chip Oscillator Control Register (Hococr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit 9.2.9 High-Speed On-Chip Oscillator Control Register (HOCOCR) Address(es): SYSTEM.HOCOCR 4001 E036h — — — — — — — HCSTP Value after reset: Symbol Bit name...
Page 130: Middle-Speed On-Chip Oscillator Control Register (Mococr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit 9.2.10 Middle-Speed On-Chip Oscillator Control Register (MOCOCR) Address(es): SYSTEM.MOCOCR 4001 E038h — — — — — — — MCSTP Value after reset: Symbol Bit name...
Page 131 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit Symbol Bit name Description b2, b1 — Reserved These bits are read as 0. MOSCSF Main Clock Oscillation 0: The main clock oscillation is stopped (MOSTP = 1) or Stabilization Flag is not stable yet 1: The main clock oscillator is stable, so is available for...
Page 132: Oscillation Stop Detection Control Register (Ostdcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit  When the PLL operates, it is deactivated when the PLLCR.PLLSTP bit is set to 1. 9.2.12 Oscillation Stop Detection Control Register (OSTDCR) Address(es): SYSTEM.OSTDCR 4001 E040h...
Page 133: Oscillation Stop Detection Status Register (Ostdsr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit 9.2.13 Oscillation Stop Detection Status Register (OSTDSR) Address(es): SYSTEM.OSTDSR 4001 E041h — — — — — — — OSTDF Value after reset: Symbol Bit name...
Page 134: Main Clock Oscillator Wait Control Register (Moscwtcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit 9.2.14 Main Clock Oscillator Wait Control Register (MOSCWTCR) Address(es): SYSTEM.MOSCWTCR 4001 E0A2h — — — — MSTS[3:0] Value after reset: Symbol Bit name Description...
Page 135: High-Speed On-Chip Oscillator Wait Control Register (Hocowtcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit 9.2.15 High-Speed On-Chip Oscillator Wait Control Register (HOCOWTCR) Address(es): SYSTEM.HOCOWTCR 4001 E0A5h — — — — — HSTS[2:0] Value after reset: Symbol Bit name Description...
Page 136: Main Clock Oscillator Mode Oscillation Control Register (Momcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit 9.2.16 Main Clock Oscillator Mode Oscillation Control Register (MOMCR) Address(es): SYSTEM.MOMCR 4001 E413h MODR — MOSEL — — — —...
Page 137: Segment Lcd Source Clock Control Register (Slcdsckcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit 9.2.18 Segment LCD Source Clock Control Register (SLCDSCKCR) Address(es): SYSTEM.SLCDSCKCR 4001 E050h LCDSC — — — — LCDSCKSEL[2:0] Value after reset: Symbol Bit name Description...
Page 138: Clock Out Control Register (Ckocr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit 9.2.19 Clock Out Control Register (CKOCR) Address(es): SYSTEM.CKOCR 4001 E03Eh CKOEN CKODIV[2:0] — CKOSEL[2:0] Value after reset: Symbol Bit name Description b2 to b0 CKOSEL[2:0]...
Page 139: Loco User Trimming Control Register (Locoutcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit 9.2.20 LOCO User Trimming Control Register (LOCOUTCR) Address(es): SYSTEM.LOCOUTCR 4001 E492h LOCOUTRM[7:0] Value after reset: Symbol Bit name Description b7 to b0 LOCOUTRM[7:0] LOCO User Trimming...
Page 140: Hoco User Trimming Control Register (Hocoutcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit When the ratio of the MOCO frequency to the other oscillation frequency is an integer value, changing the MOCOUTCR value is prohibited.
Page 141: Usb Clock Control Register (Usbckcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit 9.2.24 USB Clock Control Register (USBCKCR) Address(es): SYSTEM.USBCKCR 4001 E0D0h USBCL — — — — — — — KSEL Value after reset: Symbol Bit name...
Page 142: External Clock Input
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit 9.3.2 External Clock Input Figure 9.5 show an example of connecting an external clock input. To operate the oscillator with an external clock signal, set the MOMCR.MOSEL bit to 1.
Page 143: Connecting The Bluetooth-Dedicated Clock Output Pin
(Rf) to the oscillator is required, insert Rf between XTAL1_RF and XTAL2_RF according to the instructions. To control the oscillator, use the Bluetooth middleware provided by Renesas. The Bluetooth middleware is also able to control the settings of the on-chip variable capacitors, CL1 and CL2, to adjust the frequency of oscillation. Adjustment of the frequency of the Bluetooth-dedicated clock oscillator is explained in the application note Procedure for Adjusting the Frequency of the Bluetooth-Dedicated Clock Oscillator (R01AN4887).
Page 144 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit clock source switches to the MOCO clock.  If an oscillation stop is detected with SCKSCR.CKSEL[2:0] = 101b (system clock source = PLL), the PLL clock remains the system clock source.
Page 145: Oscillation Stop Detection Interrupts
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit Example of returning when CKSEL[2:0] = 011b (selecting the main clock oscillator) after an oscillation stop is detected. Start (Oscillation stop is detected) Switch to clock sources other than MOSC and PLL Example: Switch to SCKSCR.CKSEL[2:0] =...
Page 146: Pll Circuit
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit The oscillation stop detection interrupt is a non-maskable interrupt. Because non-maskable interrupts are disabled in the initial state after a reset release, enable the non-maskable interrupts through software before using the oscillation stop detection interrupts.
Page 147: Peripheral Module Clock (Pclka, Pclkb, Pclkc, Pclkd)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit PLLMUL[4:0] and PLODIV[1:0] bits in PLLCCR2, and the HOCOFRQ1[2:0] bits in OFS1. When the ICLK clock source is switched, the duration of the ICLK clock cycle becomes longer during the clock source transition period.
Page 148: Flash Interface Clock (Fclk)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit  CKSEL[2:0] bits in SCKSCR  PLLMUL[4:0] and PLODIV[1:0] bits in PLLCCR2  HOCOFRQ1[2:0] bits in OFS1. When the clock source of the peripheral module clock is switched, the duration of the peripheral module clock cycle becomes longer during the clock source transition period.
Page 149: Agt-Dedicated Clock (Agtsclk, Agtlclk)
9.8.14 Clocks for BLE The Bluetooth-dedicated clock (BLECLK) and the Bluetooth-dedicated low-speed clock (BLELOCO) are the operating clocks for the BLE. To control these clocks, use the Bluetooth middleware provided by Renesas. Usage Notes 9.9.1 Notes on Clock Generation Circuit The frequencies of the system clock (ICLK), peripheral module clock (PCLKA to PCLKD), and flash interface clock (FCLK) supplied to each module change according to the settings of SCKDIVCR.
Page 150: Notes On Resonator
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 9. Clock Generation Circuit 9.9.2 Notes on Resonator Because various resonator characteristics relate closely to your board design, adequate evaluation is required before use. See the resonator connection example in Figure 9.6.
Page 151: Clock Frequency Accuracy Measurement Circuit (Cac)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) Clock Frequency Accuracy Measurement Circuit (CAC) 10.1 Overview The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be measured (measurement target clock) within the time generated by the clock to be used as a measurement reference (measurement reference clock), and determines the accuracy depending on whether the number of pulses is within the allowable range.
Page 152: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) DFS[1:0] CACREFE DFS[1:0] CACREF pin Digital filter RSCS[2:0] RCDS[1:0] EDGES[1:0] 1/32 Reference 1/128 Edge detection signal circuit generation 1/1024...
Page 153: Cac Control Register 1 (Cacr1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.2 CAC Control Register 1 (CACR1) Address(es): CAC.CACR1 4004 4601h CACRE EDGES[1:0] TCSS[1:0] FMCS[2:0] Value after reset: Symbol Bit name Description...
Page 154: Cac Control Register 2 (Cacr2)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.3 CAC Control Register 2 (CACR2) Address(es): CAC.CACR2 4004 4602h DFS[1:0] RCDS[1:0] RSCS[2:0] Value after reset: Symbol Bit name Description...
Page 155: Cac Interrupt Control Register (Caicr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.4 CAC Interrupt Control Register (CAICR) Address(es): CAC.CAICR 4004 4603h OVFFC MENDF FERRF OVFIE MENDI FERRI —...
Page 156: Cac Status Register (Castr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.5 CAC Status Register (CASTR) Address(es): CAC.CASTR 4004 4604h — — — — — OVFF MENDF FERRF Value after reset: Symbol Bit name...
Page 157: Cac Upper-Limit Value Setting Register (Caulvr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.2.6 CAC Upper-Limit Value Setting Register (CAULVR) Address(es): CAC.CAULVR 4004 4606h Value after reset: CAULVR is a 16-bit read/write register that specifies the upper value of the allowable range. When the counter value rises above the value specified in this register, a frequency error is detected.
Page 158: Digital Filtering Of Signals On Cacref Pin
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) CACREF pin or internal clock CFME bit in CACR0 0 is written to 1 is written to CFME bit.
Page 159: Interrupt Requests
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 10. Clock Frequency Accuracy Measurement Circuit (CAC) selectable. The counter value transferred in CACNTBR might be in error by up to 1 cycle of the sampling clock because of the difference between the phases of the digital filter and the signal input to the CACREF pin.
Page 160: Low Power Modes
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes Low Power Modes 11.1 Overview The MCU provides several functions for reducing power consumption, such as setting clock dividers, stopping modules, selecting power control mode in normal mode, and transitioning to low power modes.
Page 161 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes Table 11.2 Operating conditions of each low power mode (2 of 2) Parameter Sleep mode Software Standby mode Snooze mode* USB 2.0 Full-Speed Module (USBFS) Selectable Stop (Retained)*...
Page 162 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes Table 11.3 Interrupt sources to transition to Normal mode from Snooze mode and Software Standby mode Interrupt source Name Software Standby mode Snooze mode VBATT...
Page 163: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes SBYCR.SSBY = 0 Reset state Sleep mode WFI instruction RES pin = High SNZCR.SNZE = 1 All interrupts Snooze mode Interrupt shown in Table 11.3 Snooze end condition...
Page 164: Module Stop Control Register A (Mstpcra)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes When the SSBY bit is set to 1, the MCU enters Software Standby mode after execution of a WFI instruction. When the MCU returns to Normal mode from Software Standby mode due to an interrupt, the SSBY bit remains 1.
Page 165 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes Symbol Bit name Description MSTPB2 Controller Area Network Target module: CAN0 Module Stop* 0: Cancel the module-stop state 1: Enter the module-stop state. b7 to b3 —...
Page 166: Module Stop Control Register C (Mstpcrc)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes 11.2.4 Module Stop Control Register C (MSTPCRC) Address(es): MSTP.MSTPCRC 4004 7004h MSTPC — — — — — — — —...
Page 167: Module Stop Control Register D (Mstpcrd)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes 11.2.5 Module Stop Control Register D (MSTPCRD) Address(es): MSTP.MSTPCRD 4004 7008h MSTPD MSTPD MSTPD MSTPD MSTPD — — — —...
Page 168: Operating Power Control Register (Opccr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes 11.2.6 Operating Power Control Register (OPCCR) Address(es): SYSTEM.OPCCR 4001 E0A0h OPCM — — — — — OPCM[1:0] Value after reset: Symbol Bit name Description...
Page 169: Snooze Control Register (Snzcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes Symbol Bit name Description b7 to b5 — Reserved These bits are read as 0. The write value should be 0. The SOPCCR register is used to reduce power consumption in Normal mode, Sleep mode, and Snooze mode.
Page 170: Snooze End Control Register (Snzedcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes RXDREQEN (RXD0 Snooze Request Enable) The RXDREQEN bit specifies whether to detect a falling edge of the RXD0 pin in Software Standby mode. This bit is only available when SCI0 operates in asynchronous mode.
Page 171: Snooze Request Control Register (Snzreqcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes section 18, Data Transfer Controller (DTC). DTCNZRED (Not Last DTC Transmission Completion Snooze End Enable) The DTCNZRED bit specifies whether to enable a transition from Snooze mode to Software Standby mode by completion of each DTC transmission, that is, CRA or CRB registers in the DTC is not 0.
Page 172 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes Symbol Bit name Description SNZREQEN7 Snooze Request Enable 7 Enable IRQ7 pin snooze request: 0: Disable the snooze request 1: Enable the snooze request.
Page 173: Flash Operation Control Register (Flstop)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes 11.2.11 Flash Operation Control Register (FLSTOP) Address(es): SYSTEM.FLSTOP 4001 E09Eh FLSTP FLSTO — — — — — — Value after reset: Symbol Bit name Description...
Page 174: System Control Ocd Control Register (Syocdcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes by setting these bits to 01b (48-KB SRAM in Software Standby mode). A WFI instruction must be executed after setting the PSMC register.
Page 175 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes range before and after switching the operating power control modes. This section provides example procedures for switching operating power control modes. Table 11.5 Available oscillators in each mode Oscillator...
Page 176: Operating Range
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes a. Invalidate the flash cache by setting FCACHEIV.FCACHEIV bit. b. Check that FCACHEIV.FCACHEIV bit is 0. c. Enable the flash cache by setting FCACHEE.FCACHEEN bit. Operation is now in Subosc-speed mode.
Page 177 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes Figure 11.2 shows the operating voltages and frequencies in High-speed mode. except P /E 0.032768 ICLK, FCLK 0.032768 ICLK, FCLK [MHz] [MHz] Note 1.
Page 178 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes Figure 11.4 shows the operating voltages and frequencies in Low-voltage mode. except P /E 0.032768 ICLK, FCLK 0.032768 ICLK, FCLK [MHz] [MHz] Figure 11.4...
Page 179: Sleep Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes Figure 11.6 shows the operating voltages and frequencies in Subosc-speed mode. 3. 6 except 2. 7 P/E is prohibited 2.
Page 180: Software Standby Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes  A WDT underflow. The operations are as follows: 1. Canceling by an interrupt When an available interrupt request is generated, Sleep mode is canceled and the MCU starts the interrupt handling. 2.
Page 181: Canceling Software Standby Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes 11.7.2 Canceling Software Standby Mode Software Standby mode is canceled by:  An available interrupt shown in Table 11.3 ...
Page 182 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes The oscillation stabilization time in Figure 11.7 is specified in section 48, Electrical Characteristics. Oscillator ICLK IRQn pin IRQMD[1:0] SBYCR.SSBY IRQ exception handling IRQ exception handling...
Page 183: Snooze Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes 11.8 Snooze Mode 11.8.1 Transition to Snooze Mode Figure 11.8 shows snooze mode entry configuration. When the snooze control circuit receives a Snooze request in Software Standby mode, the MCU transitions to Snooze mode.
Page 184: Return To Software Standby Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes Trigger Interrupt instruction detection request High Standby cancel signal Snooze end signal Software Normal Standby Low power mode mode mode Snooze mode Normal mode...
Page 185 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes Table 11.8 Snooze end conditions Snooze end request Operating module when a snooze end request occurs AGT1 underflow Other than AGT1 underflow The MCU transitions to Software Standby mode The MCU transitions to Software Standby mode after all of the modules listed to the left of this...
Page 186: Snooze Operation Example
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes 11.8.4 Snooze Operation Example Figure 11.11 shows an example setting for using ELC in Snooze mode. Start Snooze mode setting Setting for ELC in Snooze mode MSTPCRC.MSTPC14 = 0 Cancel ELC module-stop state...
Page 187 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes The MCU is capable of data transmission/reception in SCI0 asynchronous mode without CPU intervention. Table 11.9 Table 11.10 show the maximum transfer rate of the SCI0 in Snooze mode. When using the SCI0 in Snooze mode, use one of the following operating modes: ...
Page 188 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes Figure 11.12 shows an example setting for using the SCI0 in Snooze mode entry. Start Snooze mode setting Setting for SCI0 in Snooze mode MSTPCRB.MSTPB31 = 0 Cancel SCI0 module-stop state Set SCI0...
Page 189: Usage Notes
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes 11.9 Usage Notes 11.9.1 Register Access (1) Do not write to registers listed in this section in any of the following conditions: [Registers] ...
Page 190: I/O Port States
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes  SCKSCR, OPCCR. [Condition]  SOPCCR.SOPCM = 1 (Subosc-speed mode). (4) Do not write to registers listed in this section by DTC or DMAC: [Registers] ...
Page 191: Timing Of Wfi Instruction
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes 11.9.6 Timing of WFI Instruction It is possible for the WFI instruction to be executed before I/O register and CS area writes are complete, in which case operation might not proceed as intended.
Page 192: Module-Stop Function For Adc140
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 11. Low Power Modes  ADC140 window A/B compare mismatch (ADC140_WCMPUM)  Data operation circuit interrupt (DOC_DOPCI). 11.9.14 Module-Stop Function for ADC140 When entering Software Standby mode, it is recommended that you set the ADC140 module-stop state to reduce power consumption.
Page 193: Battery Backup Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 12. Battery Backup Function Battery Backup Function 12.1 Overview The MCU provides a battery backup function that maintains partial battery powering in the event of a power loss. Switching between VCC and VBATT, the battery-powered area includes RTC, SOSC, LOCO, Wakeup Control/Backup Memory, VBATT_R Low Voltage Detection, and VBATT Low Voltage Detection.
Page 194: Time Capture Pin Detection
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 12. Battery Backup Function Note: The toggle triggered by the wakeup control function does not generate an interrupt at the ICU or a reset to the reset module.
Page 195 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 12. Battery Backup Function Switch control Internal reference voltage DETBATT VBATT_R VBATT Voltage regulator for backup power Internal reference Internal reference area voltage voltage DETBATLVD VBATPOR...
Page 196: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 12. Battery Backup Function 12.2 Register Descriptions 12.2.1 VBATT Control Register 1 (VBTCR1) Address(es): SYSTEM.VBTCR1 4001 E41Fh BPWS — — — — — —...
Page 197: Vbatt Control Register 2 (Vbtcr2)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 12. Battery Backup Function 12.2.2 VBATT Control Register 2 (VBTCR2) Address(es): SYSTEM.VBTCR2 4001 E4B0h VBTLVDLVL[1:0 VBTLV — — — — — Value after reset: Symbol Bit name Description...
Page 198: Vbatt Comparator Control Register (Vbtcmpcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 12. Battery Backup Function VBTRDF flag (VBATT_R Reset Detect Flag) The VBTRDF flag indicates that a VBATT_R (selected voltage of VCC or VBATT) power-on reset occurs. [Setting condition] ...
Page 199: Vbatt Pin Low Voltage Detect Interrupt Control Register (Vbtlvdicr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 12. Battery Backup Function 12.2.5 VBATT Pin Low Voltage Detect Interrupt Control Register (VBTLVDICR) Address(es): SYSTEM.VBTLVDICR 4001 E4B4h VBTLV VBTLV — — — —...
Page 200: Vbatt Wakeup I/O 0 Output Trigger Select Register (Vbtwch0Otsr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 12. Battery Backup Function Set the VWEN bit to 1 only after setting of the following registers is complete. Set VWEN to 0 first before modifying these registers: ...
Page 201: Vbatt Output Control Register (Vbtoctlr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 12. Battery Backup Function VCH0INEN bit (VBATT Wakeup I/O n Input Enable Bit) The VCHnINEN bit defines the VBATT wakeup I/O pin input enable. You must set the VBTICTLR register when using only the VBATT wakeup control function but also the time capture function of RTC (RTCIC0).
Page 202: Vbatt Wakeup Trigger Source Edge Register (Vbtwegr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 12. Battery Backup Function b7 to b5 — Reserved These bits are read as 0. The write value should be 0. The VBTWTER register enables or disables the VBATT wakeup trigger. VBTWTER is reset by the VBATT_POR signal.
Page 203: Backup Register Access Control Register (Bkracr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 12. Battery Backup Function The VBTWFR register is initialized by VBATT_POR. VCH0F flags (VBATT Wakeup I/O 0 Wakeup Trigger Flag) These flags indicate that a trigger request by the VBATWIO0 pin is generated. [Setting condition] ...
Page 204: Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 12. Battery Backup Function To change the system clock from SOSC/LOCO to other than SOSC/LOCO: 1. Change the BKRACR.BKRACS[2:0] bits to 110b. 2. Change the SCKSCR.CKSEL[2:0] bits. 12.3 Operation 12.3.1...
Page 205: Vbatt Battery Power Supply Switch Usage
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 12. Battery Backup Function Table 12.2 Operating states in VBATT mode (2 of 2) Operating state VBATT mode Power-on reset circuit Stopped Battery backup voltage monitor Operating Other peripheral modules Stopped (undefined)
Page 206: Vbatt Pin Low Voltage Detection Procedures
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 12. Battery Backup Function 12.3.3 VBATT Pin Low Voltage Detection Procedures The VBTSR.VBTBLDF flag and interrupt can be used to monitor VBATT pin low voltage detection using the procedures described in this section.
Page 207: Vbatt Backup Register Usage
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 12. Battery Backup Function VBTCR2.VBTLVDEN, VBTCMPCR.VBTCMPE, and VBTLVDICR.VBTLVDIE. 12.3.4 VBATT Backup Register Usage The VBATT backup register VBTBKRn where n = 0 to 511, can be used to store or restore data as the following procedure describes: 1.
Page 208: Usage Notes
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 12. Battery Backup Function Vdet0 VBATTH DETBATT VBATT VBATPOR P402/VBATWIO0 Clear by I/O port powered by VCC pin software Wakeup (pulled up externally) Set by trigger software...
Page 209: Register Write Protection
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 13. Register Write Protection Register Write Protection 13.1 Overview The register write protection function protects important registers from being overwritten because of software errors. The registers to be protected are set with the Protect Register (PRCR).
Page 210: Interrupt Controller Unit (Icu)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) Interrupt Controller Unit (ICU) 14.1 Overview The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC, DTC, and DMAC modules. The ICU also controls non-maskable interrupts.
Page 211: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) Interrupt Controller CPU Stack pointer monitor MPU Bus Master error MPU Bus Slave error SRAM ECC error SRAM Parity error IWDT underflow/refresh error Clock WDT underflow/refresh error...
Page 212: Irq Control Register I (Irqcri) (I = 0 To 4, 6, 7, 9, 11, 14, 15)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) 14.2.1 IRQ Control Register i (IRQCRi) (i = 0 to 4, 6, 7, 9, 11, 14, 15) Address(es): ICU.IRQCR0 4000 6000h, ICU.IRQCR1 4000...
Page 213: Non-Maskable Interrupt Status Register (Nmisr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) IRQCRi.FLTEN bit is 1, and disabled when the IRQCRi.FLTEN bit is 0. The IRQi pin level is sampled at the cycle specified in IRQCRi.FCLKSEL[1:0].
Page 214 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) WDTST flag (WDT Underflow/Refresh Error Status Flag) This flag indicates a WDT underflow/refresh error interrupt request. It is read-only and cleared by the NMICLR.WDTCLR bit.
Page 215: Non-Maskable Interrupt Enable Register (Nmier)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) RECCST flag (SRAM ECC Error Interrupt Status Flag) This flag indicates an SRAM ECC error interrupt request. [Setting condition] ...
Page 216 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) Symbol Bit name Description VBATTEN VBATT monitor Interrupt Enable 0: Disable R/(W) *1, *2 1: Enable. ― Reserved This bit is read as 0.
Page 217: Non-Maskable Interrupt Status Clear Register (Nmiclr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) 14.2.4 Non-Maskable Interrupt Status Clear Register (NMICLR) Address(es): ICU.NMICLR 4000 6130h SPECL BUSM BUSSC RECCC RPECL NMICL OSTCL VBATT LVD1C WDTCL...
Page 218: Nmi Pin Interrupt Control Register (Nmicr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) NMICLR (NMI Clear) Writing 1 to the NMICLR bit clears the NMISR.NMIST flag. The NMICLR bit is read as 0. RPECLR (SRAM Parity Error Clear)
Page 219: Icu Event Link Setting Register N (Ielsrn)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) NFLTEN (NMI Digital Filter Enable) The NFLTEN bit enables the digital filter used for NMI pin interrupts. The filter is enabled when NFLTEN is 1 and disabled when NFLTEN is 0.
Page 220: Dmac Event Link Setting Register N (Delsrn)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) 3. Clear the IR flag by writing 0. DTCE (DTC Activation Enable) When the DTCE bit is set to 1, the associated event is selected as the source for DTC activation. [Setting condition] ...
Page 221: Sys Event Link Setting Register (Selsr0)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) 14.2.8 SYS Event Link Setting Register (SELSR0) Address(es): ICU.SELSR0 4000 6200h — — — — — — — —...
Page 222 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) Symbol Bit name Description RTCALMWUPEN RTC Alarm Interrupt 0: Disable Software standby returns by RTC alarm Software Standby Returns interrupt Enable 1: Enable Software standby returns by RTC alarm...
Page 223: Vector Table
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) USBFSWUPEN (USBFS Interrupt Software Standby Returns Enable) The USBFSWUPEN bit enables the use of USBFS interrupt to cancel Software Standby mode. AGT1UDWUPEN (AGT1 Underflow Interrupt Software Standby Returns Enable)
Page 224: Event Number
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) Table 14.3 Interrupt vector table (2 of 2) Exception number IRQ number Vector offset Source Description 05Ch ICU.IELSR7 Event selected in the ICU.IELSR7 register 060h ICU.IELSR8...
Page 225 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) Table 14.4 Event table (1 of 4) IELSRn DELSRn Canceling Event Interrupt request Connect to Invoke Canceling Software number source Name...
Page 226 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) Table 14.4 Event table (2 of 4) IELSRn DELSRn Canceling Event Interrupt request Connect to Invoke Canceling Software number source Name...
Page 227 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) Table 14.4 Event table (3 of 4) IELSRn DELSRn Canceling Event Interrupt request Connect to Invoke Canceling Software number source Name...
Page 228 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) Table 14.4 Event table (4 of 4) IELSRn DELSRn Canceling Event Interrupt request Connect to Invoke Canceling Software number source Name...
Page 229: Interrupt Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) 14.4 Interrupt Operation The ICU performs the following functions:  Detecting interrupts  Enabling and disabling interrupts  Selecting interrupt request destinations such as CPU interrupt, DTC activation, or DMAC activation. 14.4.1 Detecting Interrupts External pin interrupt requests are detected in either:...
Page 230: Selecting Interrupt Request Destinations
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) Clear the Interrupt Clear-Enable register. Clear the Interrupt Clear-Pending register as required.  When polling for interrupts: Set the Interrupt Clear-Enable register (disabling interrupts). Set the IELSRn.IELS bits (selecting the source).
Page 231: Dmac Activation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) Note 3. For chain transfers, DTC transfer continues until the last chain transfer ends. The DISEL bit state and the remaining transfer count determine whether a CPU interrupt occurs, the IELSRn.IR flag clear timing, and the interrupt request destination after transfer.
Page 232: External Pin Interrupts
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) Sampling clock for digital filter IRQCRi.FLTEN bit Pulses removed The level matches three times IRQi pin The level matches three times IRQi_d (internal F/F)
Page 233: Return From Low Power Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU)  CPU stack pointer monitor interrupt. Non-maskable interrupts can only be used with the CPU, not to activate the DTC or DMAC. Non-maskable interrupts take precedence over all other interrupts.
Page 234: Using The Wfi Instruction With Non-Maskable Interrupts
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 14. Interrupt Controller Unit (ICU) a. Set the event that you want to trigger a return to Normal mode from Snooze mode in SELSR0.SEL and set the value 017h (ICU_SNZCANCEL) in IELSRn.IELS.
Page 235: Buses
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 15. Buses Buses 15.1 Overview Table 15.1 lists the bus specifications, Figure 15.1 shows the bus configuration, and Table 15.2 lists the addresses assigned for each bus.
Page 236: Description Of Buses
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 15. Buses Table 15.2 Addresses assigned for each bus Address Area 0000 0000h to 01FF FFFFh Memory bus 1, 3 Code flash memory 2000 0000h to 2001 7FFFh Memory bus 4 SRAM0...
Page 237: Restriction On Endianness
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 15. Buses Figure 15.2 shows an example of parallel operations. In this example, the CPU uses the instruction and operand buses for simultaneous access to the flash and SRAM, respectively. Additionally, the DMAC/DTC simultaneously use the DMA bus for access to a peripheral bus during access to the flash and SRAM by the CPU.
Page 238: Slave Bus Control Register (Busscnt)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 15. Buses Table 15.3 Associations between bus types and registers Master Bus Control Slave Bus Control Bus Error Address Bus Error Status Bus type Register Register Register...
Page 239: Bus Error Address Register (Busnerradd) (N = 1 To 4)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 15. Buses Table 15.5 Round-robin priority (ARBMET[1:0] = 01b)  Slave Bus Control Register Slave interface Priority “ ”: Round-robin   BUSSCNTFLI Memory bus 1 Memory bus 3 DCode bus (CPU)
Page 240: Bus Error Monitoring Section
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 15. Buses Symbol Bit name Description ERRSTAT Bus Error Status 0: No bus error occurred 1: Bus error occurred. Note: This register is only cleared by resets other than MPU-related resets. For more information, see section 6, Resets section 16, Memory Protection Unit...
Page 241: Conditions Leading To Illegal Address Access Errors
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 15. Buses Note: The DMAC and DTC do not receive bus errors. If the DMAC or DTC accesses the bus, the transfer continues. 15.4.3 Conditions Leading to Illegal Address Access Errors Table 15.6...
Page 242: Notes On Using Flash Cache
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 15. Buses 15.5 Notes on using Flash Cache ® When using flash cache by access from the CPU, Arm MPU should also be set to cacheable. See references more information.
Page 243: Memory Protection Unit (Mpu)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) Memory Protection Unit (MPU) 16.1 Overview The MCU has four Memory Protection Units (MPUs) and a CPU stack pointer monitor function. Table 16.1 lists the supported MPU specifications, and...
Page 244 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) Table 16.3 CPU stack pointer monitor specifications (2 of 2) Parameter Description Number of regions 2 regions:  Main Stack Pointer (MSP) ...
Page 245 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) CPU processor register set Process Stack Main Stack R13 (SP) Pointer (PSP) Pointer (MSP) R14 (LR) R15 (PC) xPSR CPU stack pointer monitor Main stack pointer monitor...
Page 246: Protection Of Registers
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) Start Write Main Stack Pointer (MSP) register Write Process Stack Pointer (PSP) register Write MSPMPUSA and MSPMPUEA registers Write PSPMPUSA and PSPMPUEA registers Write MSPMPUCTL and PSPMPUCTL registers Write MSPMPUOAD and PSPMPUOAD registers...
Page 247: Main Stack Pointer (Msp) Monitor Start Address Register (Mspmpusa)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) 16.2.3.1 Main Stack Pointer (MSP) Monitor Start Address Register (MSPMPUSA) Address(es): SPMON.MSPMPUSA 4000 0D08h MSPMPUSA[31:16] Value after reset: MSPMPUSA[15:0] Value after reset: x: Undefined...
Page 248: Process Stack Pointer (Psp) Monitor Start Address Register (Pspmpusa)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) 16.2.3.3 Process Stack Pointer (PSP) Monitor Start Address Register (PSPMPUSA) Address(es): SPMON.PSPMPUSA 4000 0D18h PSPMPUSA[31:16] Value after reset: PSPMPUSA[15:0] Value after reset: x: Undefined...
Page 249: Stack Pointer Monitor Operation After Detection Register (Mspmpuoad, Pspmpuoad)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) 16.2.3.5 Stack Pointer Monitor Operation After Detection Register (MSPMPUOAD, PSPMPUOAD) Address(es): SPMON.MSPMPUOAD 4000 0D00h, SPMON.PSPMPUOAD 4000 0D10h KEY[7:0] —...
Page 250: Stack Pointer Monitor Protection Register (Mspmpupt, Pspmpupt)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU)  MSPMPUEA  MSPMPUOAD. When the PSPMPUCTL.ENABLE bit is set to 1, the following registers are available:  PSPMPUSA ...
Page 251: Arm Mpu
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) When writing to the PROTECT bit, simultaneously write A5h to the KEY[7:0] bits, using halfword access. KEY[7:0] bits (Key Code) The KEY[7:0] bits enable or disable writes to the PROTECT bit.
Page 252: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) DMAC/DTC ICode bus DCode bus System bus Bus Master MPU Group A Bus Master MPU DMA bus Data flash Internal Code flash SRAM0...
Page 253: Group A Region N Start Address Register (Mmpusan) (N = 0 To 15)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) 16.4.1.1 Group A Region n Start Address Register (MMPUSAn) (n = 0 to 15) Address(es): MMPU.MMPUSA0 4000 0204h, MMPU.MMPUSA1 4000 0214h, MMPU.MMPUSA2 4000...
Page 254 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) Symbol Bit name Description Read Protection 0: Read access permitted 1: Read access protected. Write Protection 0: Write access permitted 1: Write access protected.
Page 255: Bus Master Mpu Control Register (Mmpuctla)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) Table 16.6 Function of master control circuit Output of group A Output of group A Output of group A MMPUCTLA.ENABLE region 0 unit region 1 unit...
Page 256: Group A Protection Of Register (Mmpupta)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) 16.4.1.5 Group A Protection of Register (MMPUPTA) Address(es): MMPU.MMPUPTA 4000 0102h PROTE KEY[7:0] — — — — — —...
Page 257 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) Figure 16.5 shows the use case of a bus master MPU. MMPUCTLA. MMPUCTLA. Setting of all regions ENABLE bit = 0 ENABLE bit = 1 Setting of Protected region...
Page 258: Protecting The Registers
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) Figure 16.7 shows the register setting flow after reset. During this register setting, stop all the masters except the CPU. Start Write MMPUCTLA.OAD bit All memory is protected region...
Page 259: Bus Slave Mpu
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) the error is reported as a non-maskable interrupt or reset. The non-maskable interrupt status is indicated in ICU.NMISR.BUSMST. For details, see section 14, Interrupt Controller Unit (ICU).
Page 260: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) 16.5.1 Register Descriptions Note: Bus access must be stopped before writing to MPU registers. 16.5.1.1 Access Control Register for Memory Bus 3 (SMPUMBIU) Address(es): SMPU.SMPUMBIU 4000 0C10h...
Page 261: Access Control Register For Memory Bus 4 (Smpusram0)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) RPGRPA (Master Group A Read protection) The RPGRPA bit enables or disables memory protection for master group A reads on internal peripheral Bus 9. WPGRPA (Master Group A Write protection)
Page 262: Access Control Register For Internal Peripheral Bus 3 (Smpup2Biu)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) Symbol Bit name Description RPGRPA Master Group A Read 0: Memory protection for master group A read disabled protection 1: Memory protection for master group A read enabled.
Page 263: Access Control Register For Internal Peripheral Bus 7 (Smpup6Biu)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) 16.5.1.6 Access Control Register for Internal Peripheral Bus 7 (SMPUP6BIU) Address(es): SMPU.SMPUP6BIU 4000 0C28h WPGR RPGRP WPCP — —...
Page 264: Functions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) (Operation after detection) The OAD bit generates either a reset or non-maskable interrupt when access to the protected region is detected by the bus slave MPU.
Page 265: Register Descriptions (Option-Setting Memory)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) Table 16.8 Security MPU specifications (2 of 2) Specifications Description Protected regions 0000 0000h to 00FF FFFFh (Code flash memory) 1FF0 0000h to 200F FFFFh (SRAM) 400C 0000h to 400D FFFFh 4010 0000h to 407F FFFFh (secure data of security functions)
Page 266: Security Mpu Program Counter Start Address Register (Secmpupcsn) (N = 0, 1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) 16.6.1.1 Security MPU Program Counter Start Address Register (SECMPUPCSn) (n = 0, 1) Address(es): SECMPUPCS0 0000 0408h, SECMPUPCS1 0000 0410h SECMPUPCS[31:16] Value after reset: The value set by user...
Page 267: Security Mpu Program Counter End Address Register (Secmpupcen) (N = 0, 1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) 16.6.1.2 Security MPU Program Counter End Address Register (SECMPUPCEn) (n = 0, 1) Address(es): SECMPUPCE0 0000 040Ch, SECMPUPCE1 0000 0414h SECMPUPCE[31:16] Value after reset: The value set by user...
Page 268: Security Mpu Region 0 End Address Register (Secmpue0)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) 16.6.1.4 Security MPU Region 0 End Address Register (SECMPUE0) Address(es): SECMPUE0 0000 041Ch — — — — — —...
Page 269: Security Mpu Region 1 End Address Register (Secmpue1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) 16.6.1.6 Security MPU Region 1 End Address Register (SECMPUE1) Address(es): SECMPUE1 0000 0424h SECMPUE1[31:16] Value after reset: The value set by user SECMPUE1[15:0] Value after reset: The value set by user...
Page 270: Security Mpu Region 2 End Address Register (Secmpue2)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) 16.6.1.8 Security MPU Region 2 End Address Register (SECMPUE2) Address(es): SECMPUE2 0000 042Ch — — — — — —...
Page 271: Security Mpu Region 3 End Address Register (Secmpue3)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) 16.6.1.10 Security MPU Region 3 End Address Register (SECMPUE3) Address(es): SECMPUE3 0000 0434h — — — — — —...
Page 272: Memory Protection
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) Note: To enable or disable the security MPU, see section 16.6.2, Memory Protection. DIS0 (Region 0 Disable) The DIS0 bit enables or disables the security MPU region 0. If security MPU region 0 is enabled, the code flash region within the limits set up by the SECMPUS0 and SECMPUE0 is secure data.
Page 273: Notes On Debug
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 16. Memory Protection Unit (MPU) Security MPU setting Memory Memory Non-secure data Secure function Region 3 Secure data Non-secure data Non-secure Secure function Region 2 Secure data program...
Page 274: Dma Controller (Dmac)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) DMA Controller (DMAC) 17.1 Overview The MCU includes a 4-channel DMA Controller (DMAC) that can transfer data without intervention from the CPU. When a DMA transfer request is generated, the DMAC transfers data stored at the transfer source address to the transfer destination address.
Page 275 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) DMAC DMAC registers DMAC channels Activation control (CH0 to CH3) DMSAR DMDAR DMCRA DMA start DMCRB request transfer DMOFR request DMTMD arbitration...
Page 276: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) 17.2 Register Descriptions 17.2.1 DMA Source Address Register (DMSAR) Address(es): DMAC0.DMSAR 4000 5000h, DMAC1.DMSAR 4000 5040h, DMAC2.DMSAR 4000 5080h, DMAC3.DMSAR 4000 50C0h Value after reset: Value after reset:...
Page 277: Dma Transfer Count Register (Dmcra)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) 17.2.3 DMA Transfer Count Register (DMCRA) Address(es): DMAC0.DMCRA 4000 5008h, DMAC1.DMCRA 4000 5048h, DMAC2.DMCRA 4000 5088h, DMAC3.DMCRA 4000 50C8h ...
Page 278: Dma Block Transfer Count Register (Dmcrb)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) Setting bits [15:10] in DMCRAL is invalid. Write 0 to these bits. The value in DMCRAL is decremented by one each time data is transferred until it reaches 000h, at which time the value in DMCRAH is loaded into DMCRAL.
Page 279: Dma Interrupt Setting Register (Dmint)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) DTS[1:0] bits (Repeat Area Select) The DTS[1:0] bits select either the source or destination as the repeat area in repeat transfer mode and the block area in block transfer mode.
Page 280: Dma Address Mode Register (Dmamd)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) ESIE (Transfer Escape End Interrupt Enable) The ESIE bit enables the transfer escape end interrupt requests (repeat size end interrupt request and extended repeat area overflow interrupt request) that occur during DMA transfer.
Page 281 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) decremented by 1, 2, and 4, respectively  When offset addition is selected, the offset specified in the DMACm.DMOFR register is added to the address. SARA[4:0] bits (Source Address Extended Repeat...
Page 282: Dma Offset Register (Dmofr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) Table 17.2 SARA[4:0] or DARA[4:0] settings and corresponding repeat areas (2 of 2) SARA[4:0] or DARA[4:0] Extended repeat area 10111b 8 MB specified as extended repeat area by the lower 23 bits of the address 11000b...
Page 283: Dma Software Start Register (Dmreq)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC)  When 0 is written to this bit  When the specified total volume of data transfer is complete ...
Page 284: Dma Status Register (Dmsts)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) 17.2.11 DMA Status Register (DMSTS) Address(es): DMAC0.DMSTS 4000 501Eh, DMAC1.DMSTS 4000 505Eh, DMAC2.DMSTS 4000 509Eh, DMAC3.DMSTS 4000 50DEh — —...
Page 285: Dmac Module Activation Register (Dmast)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) flag (DMA Active Flag) The ACT flag indicates whether the DMAC is in the idle or active state. [Setting condition] ...
Page 286 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) Table 17.3 Register update operation in normal transfer mode (2 of 2) Register Function Update operation after completion of a transfer for one transfer request DMACm.DMCRAL Transfer count Decremented by one or not updated (in free running mode)
Page 287 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) Table 17.4 Register update operation in repeat transfer mode Update operation after completion of a transfer for one transfer request When DMACm.DMCRAL is 1 Register Function...
Page 288: Extended Repeat Area Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) mode, when all data in a single block is transferred, you can stop DMA transfer and request a repeat size end interrupt. To resume DMA transfer, write 1 to the DTE bit in DMACm.DMCNT during repeat size end interrupt handling.
Page 289 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) occurs in the extended repeat area on the transfer source while the SARIE bit in DMACm.DMINT is set to 1, the ESIF flag in DMACm.DMSTS is set to 1 and the DTE bit in DMACm.DMCNT is set to 0 to stop DMA transfer.
Page 290: Address Update Function Using Offset
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) Figure 17.6 shows an example of using the extended repeat area function in block transfer mode. Example: 8 bytes are specified as an extended repeat area by the lower 3 bits of DMACm.DMSAR (SARA[4:0] bits in DMACm.DMAMD = 00011b), block transfer mode with block size 5 is set (DMACm.DMCRA = 00050005h), and transfer source address is not specified as a block area.
Page 291 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) Transfer Address B1 Data 1 Address A1 Data 1 Address B2 = address B1 + 4 Data 2 Data 3 Address B3 = address B2 + 4 Offset value Data 4...
Page 292 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) First Data 1 Data 5 Data 9 Data 13 Data 1 Data 2 Data 3 Data 4 cycle Transfer Data 2 Data 6 Data 10...
Page 293 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) Figure 17.9 shows a flow of the XY conversion. Start Set the address, repeat size, and number of repeat operations Set repeat transfer mode Enable repeat size end interrupts...
Page 294: Activation Sources
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) 17.3.4 Activation Sources Software, the interrupt requests from the peripheral modules, and external interrupt requests can all be specified as DMAC activation sources.
Page 295: Execution Cycles Of Dmac
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) System clock Peripheral function interrupts or External pin interrupts DMAC activation request DMAC access Data transfer Figure 17.11 DMAC operation timing example 2 with DMA activation by interrupt from peripheral module/ external interrupt input pin, in block transfer mode with block size = 4 17.3.6 Execution Cycles of DMAC...
Page 296 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) Initial settings To use peripheral function Disable the peripheral function as the DMACm Disable the control register for the peripheral function interrupts as DMA activation request source sources...
Page 297: Starting Dma Transfer
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) 17.3.8 Starting DMA Transfer To enable a DMA transfer of channel m, set the DTE bit in DMACm.DMCNT to 1 (DMA transfer enabled) and set the DMST bit in DMAST to 1 (DMAC start enabled).
Page 298: Channel Priority
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) is requested. When this bit and the ESIE bit in DMACm.DMINT are 1, a transfer escape end interrupt is requested. This flag is set to 1 when the bus cycle of the DMA transfer that caused the interrupt request is complete and the ACT flag in DMACm.DMSTS is set to 0, indicating the DMA transfer end.
Page 299: Precautions For The End Of Dma Transfer
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) If this interrupt is requested during a read cycle, the subsequent write cycle is performed. In block transfer mode, if the interrupt is requested during a 1-block transfer, the remaining data in the block is transferred before transfer stops.
Page 300: Event Link
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) Different procedures are used for canceling an interrupt to restart a DMA transfer in the following cases:  When terminating a DMA transfer ...
Page 301: Usage Notes
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 17. DMA Controller (DMAC) (2) Software Standby mode Use the settings described in section 11.7.1, Transition to Software Standby Mode. If DMA transfer operations are in progress when the WFI instruction is executed, the DMA transfer completes before the transition to Software Standby mode.
Page 302: Data Transfer Controller (Dtc)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) Data Transfer Controller (DTC) 18.1 Overview The MCU includes a Data Transfer Controller (DTC) that performs data transfers when activated by an interrupt request. Table 18.1 lists the DTC specifications and Figure 18.1...
Page 303: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) C P U N o n -m a s k a b le in te rru p t re q u e s t N V IC In te rru p t re q u e s t A c tiv a tio n re q u e s t...
Page 304: Dtc Mode Register A (Mra)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) 18.2.1 DTC Mode Register A (MRA) Address(es): (inaccessible directly from the CPU. See section 18.3.1) MD[1:0] SZ[1:0] SM[1:0] —...
Page 305: Dtc Transfer Source Register (Sar)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) Symbol Bit name Description b3, b2 DM[1:0] Transfer Destination Address — b3 b2 0 0: Address in the DAR register is fixed Addressing Mode (write-back to DAR is skipped) 0 1: Address in the DAR register is fixed...
Page 306: Dtc Transfer Destination Register (Dar)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) access the SRAM area (transfer information (n) start address + 04h) and the DTC automatically transfers the transfer information to and from the SAR register.
Page 307: Dtc Transfer Count Register B (Crb)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) register. See section 18.3.1, Allocating Transfer Information and DTC Vector Table. (1) Normal transfer mode (MRA.MD[1:0] bits = 00b) In normal transfer mode, CRA functions as a 16-bit transfer counter.
Page 308: Dtc Vector Base Register (Dtcvbr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) When the transfer counter (CRA register) becomes 0 during the previous normal transfer and when the transfer counter (CRB register) becomes 0 during the previous block transfer, the transfer information is read regardless of the RRS bit value.
Page 309: Dtc Status Register (Dtcsts)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) 18.2.10 DTC Status Register (DTCSTS) Address(es): DTC.DTCSTS 4000 540Eh — — — — — — — VECN[7:0] Value after reset: Symbol Bit name Description...
Page 310: Allocating Transfer Information And Dtc Vector Table
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) 18.3.1 Allocating Transfer Information and DTC Vector Table The DTC reads the start address of the transfer information associated with each activation source from the vector table and reads the transfer information starting at that address.
Page 311: Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) Allocation of transfer information Lower address Start address Reserved (0) Transfer information per transfer (4 words (16 bytes)) Chain transfer Reserved (0)
Page 312 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) Setting the MRB.CHNE bit to 1 allows multiple transfers or chain transfer on a single activation source. It also enables a chain transfer when the specified data transfer is complete.
Page 313: Transfer Information Read Skip Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) Table 18.3 Chain transfer conditions First transfer Second transfer* CHNE CHNS DISEL Transfer CHNE CHNS DISEL Transfer counter* counter* DTC transfer —...
Page 314: Normal Transfer Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) Table 18.4 Transfer information write-back skip conditions and applicable registers MRA.SM[1:0] bits MRB.DM[1:0] bits SAR register DAR register Skip Skip Skip...
Page 315: Repeat Transfer Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) Transfer source data area Transfer destination data area Transfer 6 times Data 1 Data 1 (transfer 1 data per each event) Data 2 Data 2...
Page 316: Block Transfer Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) Transfer source data area Transfer destination data area (set to repeat area) Transfer 8 times Data 1 Data 1 (transfer 1 data per each event) Data 2...
Page 317: Chain Transfer
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) Transfer source data area Transfer destination data area (set to block area) First block Transfer Block area nth block Figure 18.7 Memory map of block transfer mode 18.4.6...
Page 318: Operation Timing
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) Writing 1 to the MRB.CHNE and CHNS bits enables chain transfer to be performed only after completion of the specified data transfer.
Page 319 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) System clock ICU.IELSRn.IR DTC activation request DTC access Data Transfer Data Transfer Transfer Transfer Vector read transfer transfer information read information information...
Page 320: Execution Cycles Of Dtc
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) 18.4.8 Execution Cycles of DTC Table 18.8 lists the execution cycles of single data transfer of the DTC. For the order of the execution states, see section 18.4.7, Operation Timing.
Page 321: Examples Of Dtc Usage
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) Start Set the ICU.IELSRn.IELS[7:0] bit to 0 to disable the interrupt in the NVIC and provide the following settings: Set the DTCCR.RRS bit to 0 [1] Set the DTCCR.RRS bit to 0 to reset the transfer information read skip flag.
Page 322: Chain Transfer
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) (2) DTC vector table settings The start address of the transfer information for the RXI interrupt is set in the vector table for the DTC. (3) ICU settings and DTC module activation Set the ICU.IELSRn.DTCE bit to 1 and set ICU.IELSRn.IELS as the SCI interrupt.
Page 323 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) 4. Set the SAR register to the first address of the data table. 5. Set the DAR register to the address of the GPT320.GTCCRE register. 6.
Page 324: Chain Transfer When Counter = 0
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) 18.6.3 Chain Transfer when Counter = 0 The second data transfer is performed only when the transfer counter is set to 0 in the first data transfer, and the first data transfer information is repeatedly changed in the second transfer.
Page 325: Interrupt Source
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) Input circuit Transfer information allocated in the on-chip memory space Input buffer First data transfer Transfer information Chain transfer (counter = 0) Second data transfer Transfer information...
Page 326: 18.11 Usage Notes
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 18. Data Transfer Controller (DTC) (2) Software Standby mode Use the settings described in section 11.7.1, Transition to Software Standby Mode. If DTC transfer operations are in progress when the WFI instruction is executed, the transition to Software Standby mode follows the completion of the DTC transfer.
Page 327: Event Link Controller (Elc)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 19. Event Link Controller (ELC) Event Link Controller (ELC) 19.1 Overview The Event Link Controller (ELC) uses the event requests generated by various peripheral modules as source signals to connect them to different modules, allowing direct link between the modules without CPU intervention.
Page 328: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 19. Event Link Controller (ELC) 19.2 Register Descriptions 19.2.1 Event Link Controller Register (ELCR) Address(es): ELC.ELCR 4004 1000h ELCON — — — — —...
Page 329: Event Link Setting Register N (Elsrn) (N = 0 To 9, 12, 14 To 18)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 19. Event Link Controller (ELC) 19.2.3 Event Link Setting Register n (ELSRn) (n = 0 to 9, 12, 14 to 18) Address(es): ELC.ELSR0 4004 1010h, ELC.ELSR1 4004 1014h,...
Page 330 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 19. Event Link Controller (ELC) Table 19.3 Association between event signal names set in ELSRn.ELS bits and signal numbers (1 of 4) Event number Interrupt request source Name Description...
Page 331 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 19. Event Link Controller (ELC) Table 19.3 Association between event signal names set in ELSRn.ELS bits and signal numbers (2 of 4) Event number Interrupt request source Name Description...
Page 332 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 19. Event Link Controller (ELC) Table 19.3 Association between event signal names set in ELSRn.ELS bits and signal numbers (3 of 4) Event number Interrupt request source Name Description...
Page 333: Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 19. Event Link Controller (ELC) Table 19.3 Association between event signal names set in ELSRn.ELS bits and signal numbers (4 of 4) Event number Interrupt request source Name Description...
Page 334: Usage Notes
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 19. Event Link Controller (ELC) 3. Set the ELCR.ELCON bit to 1 to enable linkage of all events. 4. Configure the module from which an event is output and activate the module. The link between the two modules is now active.
Page 335: I/O Ports
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports I/O Ports 20.1 Overview The I/O port pins operate as general I/O port pins, I/O pins for peripheral modules, interrupt input pins, analog I/O, port group function for ELC, or bus control pins.
Page 336: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports Table 20.1 I/O port specifications (2 of 2) Port Port name Number of pins PORT5 P501 PORT9 P914, P915 : available ...
Page 337: Port Control Register 2 (Pcntr2/Eidr/Pidr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports The Port Control Register 1 (PCNTR1/PODR/PDR) is a 32-bit and 16-bit read/write register that controls the port direction and port output data. The PCNTR1 specifies the port direction and output data, and is accessed in 32-bit units.
Page 338: Port Control Register 3 (Pcntr3/Porr/Posr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports A pin state cannot be reflected in PIDRn when one of the following functions is enabled:  Main clock oscillator (MOSC) ...
Page 339: Port Control Register 4 (Pcntr4/Eorr/Eosr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports be 0. P200, P214, and P215 are input only, so PORT2.PCNTR3.PORR00, PORT2.PCNTR3.PORR14, and PORT2.PCNTR3.PORR15 are reserved. 20.2.4 Port Control Register 4 (PCNTR4/EORR/EOSR) Address(es): PORT1.PCNTR4 4004...
Page 340: Port Mn Pin Function Select Register (Pmnpfs/Pmnpfs_Ha/Pmnpfs_By)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports 20.2.5 Port mn Pin Function Select Register (PmnPFS/PmnPFS_HA/PmnPFS_BY) (m = 0 to 5, 9; n = 00 to 15) Address(es): PFS.P004PFS 4004 0810h, PFS.P010PFS 4004...
Page 341 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports Symbol Bit name Description Port Mode Control 0: Used as a general I/O pin 1: Used as an I/O port for peripheral functions. b23 to b17 —...
Page 342: Write-Protect Register (Pwpr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports 20.2.6 Write-Protect Register (PWPR) Address(es): PMISC.PWPR 4004 0D03h B0WI PFSWE — — — — — — Value after reset: Symbol Bit name Description b5 to b0...
Page 343: Port Group Function For The Elc
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports  PCR: Pull-up resistor control bit that turns the input pull-up MOS on or off  NCODR: N-channel open-drain control bit that selects the output type for each pin ...
Page 344: Behavior When An Event Pulse Is Output To The Elc
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports EOSR PODR EORR ELC_PORT1, 2, 3, or 4 Figure 20.3 Event ports output data 20.3.3.2 Behavior when an event pulse is output to the ELC To output the event pulse from the external pins to the ELC, set the EOR/EOF bits in the PmnPFS register.
Page 345: Handling Of Unused Pins
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports 20.4 Handling of Unused Pins Table 20.3 shows how to handle unused pins. Table 20.3 Handling of unused pins Pin name Description P201/MD Use as a mode pin...
Page 346: Port Output Data Register (Podr) Summary
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports 20.5.3 Port Output Data Register (PODR) Summary This register outputs data as follows: 1. Output 0 if PCNTR4.EORRn is set to 1 when an ELC_PORT1, 2, 3, or 4 signal occurs. 2.
Page 347: Pull-Up/Pull-Down Setting For P914 And P915 Using Usbfs/Gpio Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports 20.5.7 Pull-up/Pull-down Setting for P914 and P915 using USBFS/GPIO Function When P914 and P915 are used as GPIO pins, their operation is affected by the pull-up/pull-down function of the USBFS registers.
Page 348 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports Table 20.6 Register settings for I/O pin functions (PORT1) (1) PSEL[4:0] bit settings Function P100 P101 P102 P103 P104 P105 P106 P107 00000b (value...
Page 349 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports Table 20.7 Register settings for I/O pin functions (PORT1) (2) PSEL[4:0] bit settings Function P108 P109 P110 P111 00000b (value Hi-Z/JTAG/SWD TMS/ TDO/...
Page 350 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports Table 20.8 Register settings for I/O pin functions (PORT2) (1) PSEL[4:0] bit settings Function P200 P201 P204 P205 P206 00000b (value Hi-Z/JTAG/SWD Hi-Z after reset)
Page 351 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports Table 20.9 Register settings for I/O pin functions (PORT2) (2) PSEL[4:0] bit settings Function P212 P213 P214 P215 00000b (value Hi-Z/JTAG/SWD Hi-Z after reset)
Page 352 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports Table 20.10 Register settings for I/O pin functions (PORT3) PSEL[4:0] bit settings Function P300 00000b (value Hi-Z/JTAG/SWD TCK/ after reset) SWCLK 00001b ―...
Page 353 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports Table 20.12 Register settings for I/O pin functions (PORT4) (2) PSEL[4:0] bit settings Function P409 P414 00000b (value Hi-Z/JTAG/SWD Hi-Z after reset) 00001b ―...
Page 354 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 20. I/O Ports Table 20.13 Register settings for I/O pin functions (PORT5) PSEL[4:0] bit settings Function P501 00000b (value Hi-Z/JTAG/SWD Hi-Z after reset) 00001b AGTOB0 00010b...
Page 355: Key Interrupt Function (Kint)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 21. Key Interrupt Function (KINT) Key Interrupt Function (KINT) 21.1 Overview A key interrupt (KEY_INTKR) can be generated by setting the Key Return Mode register (KRM) and inputting a rising or falling edge to the key interrupt input pins, KR00 to KR07.
Page 356 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 21. Key Interrupt Function (KINT) Filter KR00 KRF0 KREG KRM0 KRMD Filter KR01 KRF1 KREG KRM1 KRMD Filter KR02 KRF2 KREG KRM2 KRMD Filter KR03 KRF3...
Page 357: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 21. Key Interrupt Function (KINT) 21.2 Register Descriptions 21.2.1 Key Return Control Register (KRCTL) Address(es): KINT.KRCTL 4008 0000h KRMD — — — — —...
Page 358: Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 21. Key Interrupt Function (KINT) Note: The on-chip pull-up resistors can be applied by setting the associated key interrupt input pin in the pull-up resistor. For details, section 20, I/O Ports.
Page 359 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 21. Key Interrupt Function (KINT) the key interrupt (KEY_INTKR) is generated. If the KRMD bit is set to 1, clear the KEY_INTKR signal by clearing the associated bit in the KRF register.
Page 360: Usage Notes
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 21. Key Interrupt Function (KINT) KR00 KR01 KR05 KRF0 Cleared by software Delay time KRF1 Cleared by software Delay time KRF5 Cleared by software Delay time KEY_INTKR...
Page 361: Port Output Enable For Gpt (Poeg)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 22. Port Output Enable for GPT (POEG) Port Output Enable for GPT (POEG) 22.1 Overview The Port Output Enable (POEG) can place the General PWM Timer (GPT) output pins in the output-disable state in one of the following ways: ...
Page 362: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 22. Port Output Enable for GPT (POEG) Group B POEG Group A IOCF IOCE Ch 0 POEG_GROUP0 POEG_GROUP1 Group A Ch 0 GTINTAD.GRPABH, GTINTAD.GRPABL Group B Ch 8...
Page 363: Output-Disable Control Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 22. Port Output Enable for GPT (POEG) Symbol Bit name Description IOCF Output-disable Request 0: No output-disable request from the GPT disable request R(/W)* Detection Flag from GPT occurred...
Page 364: Pin Input Level Detection Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 22. Port Output Enable for GPT (POEG) 22.3.1 Pin Input Level Detection Operation If the input conditions set by POEGGn.PIDE, POEGGn.NFCS[1:0], POEGGn.NFEN, and POEGGn.INV occur on the GTETRGn pins, the GPT output pins are output-disabled.
Page 365: Interrupt Sources
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 22. Port Output Enable for GPT (POEG) flags in GPT are set to 0. Writing 0 to the POEGGn.OSTPF flag is ignored (the flag is not cleared) if the OSTDSR.OSTDF flag in the clock generation circuit is not set to 0.
Page 366: Usage Notes
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 22. Port Output Enable for GPT (POEG)  Down-count  Input capture. For the POEGG.INV polarity setting signal, when the same level is input three times continuously with the sampling clock selected in the POEGGn.NFCS[1:0] and POEGGn.NFEN bits, that value is output.
Page 367: General Pwm Timer (Gpt)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) General PWM Timer (GPT) 23.1 Overview The General PWM Timer (GPT) is a 32-bit timer with four GPT32 channels, and a 16-bit timer with three GPT16 channels.
Page 368 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Table 23.2 GPT functions Parameter GPT32, GPT16 Count clock PCLKD PCLKD/4 PCLKD/16 PCLKD/64 PCLKD/256 PCLKD/1024 Output compare/input capture registers (GTCCR) GTCCRA GTCCRB Compare/buffer registers...
Page 369 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) G P T320 Control registers Interrupt request signals G P T321 G PT0_CC M PA G TW P G TIC ASR G TD TCR G P T322...
Page 370 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Table 23.3 lists the I/O pins used in the GPT. Table 23.3 GPT I/O pins Channel Pin name Function Shared GTETRGA...
Page 371: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) 23.2 Register Descriptions Table 23.4 lists the registers in the GPT. Table 23.4 GPT registers Module Register Access symbol Register name symbol...
Page 372: General Pwm Timer Write-Protection Register (Gtwp)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) 23.2.1 General PWM Timer Write-Protection Register (GTWP) Address(es): GPT32m.GTWP 4007 8000h + 0100h × m (m = 0 to 3), GPT16m.GTWP 4007 8000h + 0100h ×...
Page 373: General Pwm Timer Software Stop Register (Gtstp)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) 23.2.3 General PWM Timer Software Stop Register (GTSTP) Address(es): GPT32m.GTSTP 4007 8008h + 0100h × m (m = 0 to 3), GPT16m.GTSTP 4007 8008h + 0100h ×...
Page 374: General Pwm Timer Start Source Select Register (Gtssr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) 23.2.5 General PWM Timer Start Source Select Register (GTSSR) Address(es): GPT32m.GTSSR 4007 8010h + 0100h × m (m = 0 to 3), GPT16m.GTSSR 4007 8010h + 0100h ×...
Page 375 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description SSCBFAL GTIOCB Pin Falling Input during 0: Counter start disabled on the falling edge of GTIOCB GTIOCA Value Low Source input when GTIOCA input is 0 Counter Start Enable...
Page 376: General Pwm Timer Stop Source Select Register (Gtpsr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) SSCAFBH (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable) The SSCAFBH bit enables or disables the GTCNT counter start on the falling edge of GTIOCA pin input, when GTIOCB input is 1.
Page 377 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description PSGTRGBF GTETRGB Pin Falling Input Source 0: Counter stop disabled on the falling edge of GTETRGB Counter Stop Enable input 1: Counter stop enabled on the falling edge of GTETRGB...
Page 378 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) PSGTRGAR (GTETRGA Pin Rising Input Source Counter Stop Enable) The PSGTRGAR bit enables or disables the GTCNT counter stop on the rising edge of GTETRGA pin input. PSGTRGAF (GTETRGA Pin Falling Input Source Counter Stop Enable)
Page 379: General Pwm Timer Clear Source Select Register (Gtcsr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) 23.2.7 General PWM Timer Clear Source Select Register (GTCSR) Address(es): GPT32m.GTCSR 4007 8018h + 0100h × m (m = 0 to 3), GPT16m.GTCSR 4007 8018h + 0100h ×...
Page 380 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description CSCBFAL GTIOCB Pin Falling Input during 0: Counter clear disabled on the falling edge of GTIOCB GTIOCA Value Low Source input when GTIOCA input is 0 Counter Clear Enable...
Page 381: General Pwm Timer Up Count Source Select Register (Gtupsr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) CSCAFBH (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable) The CSCAFBH bit enables or disables GTCNT counter clear on the falling edge of GTIOCA pin input, when GTIOCB input is 1.
Page 382 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description USGTRGBF GTETRGB Pin Falling Input Source 0: Counter count up disabled on the falling edge of Counter Count Up Enable GTETRGB input 1: Counter count up enabled on the falling edge of...
Page 383 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) USGTRGAR (GTETRGA Pin Rising Input Source Counter Count Up Enable) The USGTRGAR bit enables or disables the GTCNT counter count up on the rising edge of GTETRGA pin input. USGTRGAF (GTETRGA Pin Falling Input Source Counter Count Up Enable)
Page 384: General Pwm Timer Down Count Source Select Register (Gtdnsr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) 23.2.9 General PWM Timer Down Count Source Select Register (GTDNSR) Address(es): GPT32m.GTDNSR 4007 8020h + 0100h × m (m = 0 to 3), GPT16m.GTDNSR 4007 8020h + 0100h ×...
Page 385 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description DSCBFAL GTIOCB Pin Falling Input during 0: Counter count down disabled on the falling edge of GTIOCA Value Low Source GTIOCB input when GTIOCA input is 0 Counter Count Down Enable...
Page 386: General Pwm Timer Input Capture Source Select Register A(Gticasr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GTIOCB input is 0. DSCAFBH (GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable) The DSCAFBH bit enables or disables the GTCNT counter count down on the falling edge of GTIOCA pin input, when GTIOCB input is 1.
Page 387 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description ASGTRGBR GTETRGB Pin Rising Input Source 0: GTCCRA input capture disabled on the rising edge of GTCCRA Input Capture Enable GTETRGB input 1: GTCCRA input capture enabled on the rising edge of...
Page 388 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) The GTICASR sets the source of input capture for GTCCRA. ASGTRGAR (GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable) The ASGTRGAR bit enables or disables input capture for GTCCRA on the rising edge of GTETRGA pin input.
Page 389: General Pwm Timer Input Capture Source Select Register B(Gticbsr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) 23.2.11 General PWM Timer Input Capture Source Select Register B(GTICBSR) Address(es): GPT32m.GTICBSR 4007 8028h + 0100h × m (m = 0 to 3), GPT16m.GTICBSR 4007 8028h + 0100h ×...
Page 390 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description BSCBFAL GTIOCB Pin Falling Input during 0: GTCCRB input capture disabled on the falling edge of GTIOCA Value Low Source GTIOCB input when GTIOCA input is 0 GTCCRB Input Capture Enable...
Page 391: General Pwm Timer Control Register (Gtcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) BSCAFBH (GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable) The BSCAFBH bit enables or disables input capture for GTCCRB on the falling edge of GTIOCA pin input, when GTIOCB input is 1.
Page 392 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description b18 to b16 MD[2:0] Mode Select 0 0 0: Saw-wave PWM mode (single buffer or double buffer possible) 0 0 1: Saw-wave one-shot pulse mode (fixed buffer operation)
Page 393: General Pwm Timer Count Direction And Duty Setting Register (Gtuddtyc)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) 23.2.13 General PWM Timer Count Direction and Duty Setting Register (GTUDDTYC) Address(es): GPT32m.GTUDDTYC 4007 8030h + 0100h × m (m = 0 to 3), GPT16m.GTUDDTYC 4007 8030h + 0100h ×...
Page 394 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) becomes GTPR value). When the UD value changes from 0 to 1 with the UDF bit being 0 and while counting stops, the counter starts down-counting and the count direction changes at an underflow (the timing synchronous with count clock after GTCNT value becomes 0).
Page 395: General Pwm Timer I/O Control Register (Gtior)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) 23.2.14 General PWM Timer I/O Control Register (GTIOR) Address(es): GPT32m.GTIOR 4007 8034h + 0100h × m (m = 0 to 3), GPT16m.GTIOR 4007 8034h + 0100h ×...
Page 396 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description b31, b30 NFCSB[1:0] Noise Filter B Sampling Clock b31 b30 0 0: PCLKD/1 Select 0 1: PCLKD/4 1 0: PCLKD/16 1 1: PCLKD/64.
Page 397 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT)  The value specified in bit [4] of the GTIOB[4:0] bits is output when counting starts  The value specified in the OBDFLT bit is output when counting stops ...
Page 398: General Pwm Timer Interrupt Output Setting Register (Gtintad)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Table 23.5 Settings of GTIOA[4:0] and GTIOB[4:0] bits (2 of 2) GTIOA/GTIOB[4:0] bits Function b3, b2* b1, b0* Initial output is high Output retained at Output retained at GTCCRA/GTCCRB compare match...
Page 399: General Pwm Timer Status Register (Gtst)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description GRPABH Same Time Output Level High Disable 0: Same time output level high disable request Request Enable disabled 1: Same time output level high disable request...
Page 400 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description TCFF Input Compare Match Flag F 0: No compare match of GTCCRF is generated R/(W)* 1: A compare match of GTCCRF is generated.
Page 401 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT)  GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)  GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)  GTBER.CCRA[1:0] = 01b, 10b, 11b (GTCCRC performs buffer operation). TCFD flag (Input Compare Match Flag...
Page 402 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT)  In counting by hardware sources, an overflow (GTCNT changes from GTPR to 0 in up-counting) has occurred. [Clearing condition] ...
Page 403: General Pwm Timer Buffer Enable Register (Gtber)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT)  The GTIOCA and GTIOCB pins output 1 at the same time when both OAE and OBE bits are set to 1 ...
Page 404: General Pwm Timer Counter (Gtcnt)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) CCRA[1:0] bits (GTCCRA Buffer Operation) The CCRA[1:0] bits set buffer operation using GTCCRA, GTCCRC, and GTCCRD combined. When buffer operation is restricted by the operating mode set in GTCR, the GTCR setting is given priority.
Page 405: General Pwm Timer Compare Capture Register N (Gtccrn) (N = A To F)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) 23.2.19 General PWM Timer Compare Capture Register n (GTCCRn) (n = A to F) Address(es): GPT32m.GTCCRA 4007 804Ch + 0100h × m (m = 0 to 3), GPT16m.GTCCRA 4007 804Ch + 0100h ×...
Page 406: General Pwm Timer Cycle Setting Buffer Register (Gtpbr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) 23.2.21 General PWM Timer Cycle Setting Buffer Register (GTPBR) Address(es): GPT32m.GTPBR 4007 8068h + 0100h × m (m = 0 to 3), GPT16m.GTPBR 4007 8068h + 0100h ×...
Page 407: General Pwm Timer Dead Time Value Register U (Gtdvu)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Lower limit value: 0. 23.2.23 General PWM Timer Dead Time Value Register U (GTDVU) Address(es): GPT32m.GTDVU 4007 808Ch + 0100h x m (m = 0 to 3), GPT16m.GTDVU 4007 808Ch + 0100h x m (m = 4, 5, 8) Value after reset: Value after reset:...
Page 408 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Symbol Bit name Description External Feedback Signal Enable This bit selects the input phase from software settings and external input: 0: Select the external input 1: Select the soft setting (OPSCR.UF, VF, WF).
Page 409: Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) (GTOUUP pin, GTOVUP pin, GTOWUP pin). (Negative-Phase Output (N) Control) The N bit selects one of the level signal output (PWM of GPT320) or PWM signal output for the negative-phase output (GTOULO pin, GTOVLO pin, GTOWLO pin).
Page 410 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT)  Writing to GTCR register  Writing 1 to the bit in GTSTR associated with the GPT channel number when the GTSSR.CSTRT bit is set to 1 ...
Page 411 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.3, 000b (saw-wave PWM mode) is set.) Set count direction Select the count direction with the GTUDDTYC register.
Page 412 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.5, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction with the GTUDDTYC register.
Page 413 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) PCLKD GTETRGA N + 1 GTCNT Figure 23.7 Example of periodic count operation in up-counting using hardware sources Figure 23.8 shows an example for setting periodic count operation in down-counting by the count clock.
Page 414 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) PCLKD GTETRGA N + 1 GTCNT Figure 23.9 Example of event count operation in down-counting using hardware sources Figure 23.10 shows an example for setting a periodic count operation in down-counting using a hardware resource.
Page 415: Waveform Output By Compare Match
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) 23.3.1.2 Waveform output by compare match Compare match means that the GTCNT counter value matches the value of GTCCRA or GTCCRB. When a compare match occurs, the compare match flag is generated synchronously with the count clock including the event count.
Page 416 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Figure 23.12 shows an example for setting low output and high output operation. Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.11, 000b (saw-wave PWM mode) is set.
Page 417 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register GPT320.GTCCRB register GPT320.GTCCRA register 0000 0000h Time GTIOC0A pin output GTIOC0B pin output [Setting examples] GPT320.GTIOR.GTIOA[4:0] bits: Initial output is high, output toggled at compare match, output retained at cycle end GPT320.GTIOR.GTIOB[4:0] bits: Initial output is low, output toggled at compare match, output retained at cycle end...
Page 418: Input Capture Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Figure 23.15 shows an example setting for toggled output operation. Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.13 Figure 23.14, 000b (saw-wave PWM mode) is set.
Page 419 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register E400h C154h 9682h 1100h Time 0000 0000h GTIOC0A pin input GTIOC0B pin input GPT320.GTCCRA register 9682h E400h...
Page 420: Buffer Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.16, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register.
Page 421 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GTCNT counter value cccc bbbb aaaa 0000 0000h Time Register write Register write Register write Register write GTPBR register bbbb cccc Buffer transfer...
Page 422 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GTCNT counter value cccc bbbb aaaa 0000 0000h Time GTPBR register aaaa bbbb cccc Buffer transfer at trough Buffer transfer at trough Buffer transfer at trough GTPR register...
Page 423: Buffer Operation For Gtccra And Gtccrb
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.18 Figure 23.19 000b (saw-wave PWM mode) is set, and in Figure 23.20 100b (triangle-wave PWM mode 1) is set.
Page 424 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT)  Buffer transfer by overflow or underflow Buffer transfer is performed at an overflow (during up-counting) or an underflow (during down-counting) in saw- wave mode or in event count operation.
Page 425 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register cccc bbbb aaaa 0000 0000h Time Register write Register write Register write GPT320.GTCCRD register cccc Buffer transfer at Buffer transfer at...
Page 426 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.22, 000b (saw-wave PWM mode) is set, in Figure 23.23, 100b (triangle-wave PWM mode 1) is set, and in Figure...
Page 427 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Figure 23.26 Figure 23.27 show examples of GTCCRA and GTCCRB buffer operation and Figure 23.28 shows an example for setting the GTCCRA and GTCCRB buffer operation. GPT320.GTCNT counter value GPT320.GTPR register cccc...
Page 428: Pwm Output Operating Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0] and count clear source with GTCSR. Figure 23.26, MD[2:0] = 000b (saw-wave PWM mode) and GTCSR = 0000 0F00h, and in Figure 23.27, MD[2:0] = 000b (saw-wave PWM mode) and GTCSR = 0000 F000h.
Page 429 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register ffff eeee dddd cccc bbbb aaaa 0000 0000h Time Register write Register write Register write Register write GPT320.GTCCRC register...
Page 430 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. In Figure 23.29, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register.
Page 431: Saw-Wave One-Shot Pulse Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) 23.3.3.2 Saw-wave one-shot pulse mode The saw-wave one-shot pulse mode is a mode in which the cycle is set in GTPR. The GTCNT counter performs saw- wave (half-wave) operation and a PWM waveform is output to the GTIOCA or GTIOCB pin at a compare match of GTCCRA or GTCCRB with buffer operation fixed.
Page 432 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register hhhh gggg ffff eeee dddd cccc bbbb aaaa 0000 0000h Time Register write Register write Register write GPT320.GTCCRD register...
Page 433: Triangle-Wave Pwm Mode 1 (32-Bit Transfer At Trough)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.31, 001b (saw-wave one-shot pulse mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register.
Page 434 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) low output, high output, or toggle output separately for a compare match and for the cycle end based on the GTIOR setting.
Page 435 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.33, 100b (triangle-wave PWM mode 1) is set. Select count clock Select the count clock with GTCR.TPCS[2:0].
Page 436: Triangle-Wave Pwm Mode 2 (32-Bit Transfer At Crest And Trough)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) 23.3.3.4 Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) Similar to triangle-wave PWM mode 1, in triangle-wave PWM mode 2 the cycle is set in GTPR. The GTCNT counter performs triangle-wave (full-wave) operation, and a PWM waveform is output to the GTIOCA or GTIOCB pin when a GTCCRA or GTCCRB compare match occurs.
Page 437 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.35, 101b (triangle-wave PWM mode 2) is set. Select count clock Select the count clock with GTCR.TPCS[2:0].
Page 438: Triangle-Wave Pwm Mode 3 (64-Bit Transfer At Trough)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) 23.3.3.5 Triangle-wave PWM mode 3 (64-bit transfer at trough) The triangle-wave PWM mode 3 is a mode in which the cycle is set in GTPR. The GTCNT counter performs triangle- wave (full-wave) operation and a PWM waveform is output to the GTIOCA or GTIOCB pin at a compare match of GTCCRA or GTCCRB with buffer operation fixed.
Page 439 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register hhhh gggg ffff eeee dddd cccc bbbb aaaa 0000 0000h Time Register write Register write GPT320.GTCCRD register hhhh...
Page 440: Automatic Dead Time Setting Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.37, 110b (triangle-wave PWM mode 3) is set. Select count clock Select the count clock with GTCR.TPCS[2:0].
Page 441 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Figure 23.39 Figure 23.42 show examples of automatic dead time setting function operation. Figure 23.43 Figure 23.44 show the setting examples. GPT320.GTCNT counter value GPT320.GTPR register GPT320.GTCCRA register...
Page 442 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register GPT320.GTCCRA register Time 0000 0000h Buffer transfer at trough Buffer transfer at trough GPT320.GTCCRA register GPT320.GTCCRB register GTCCRA - GTDVU...
Page 443 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. In Figure 23.39 Figure 23.40, 001b (saw-wave one-shot pulse mode) is set.
Page 444: Count Direction Changing Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. In Figure 23.41, 100b (triangle-wave PWM mode 1) is set. In Figure 23.42, 101b (triangle-wave PWM mode 2) is set.
Page 445: Function Of Output Duty 0% And 100
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) and GTUDDTYC.UDF bit is 0, the GTUDDTYC.UD bit value is not reflected to the count operation. If the GTUDDTYC.UDF bit is set to 1 while the count operation is stopped, the GTUDDTYC.UD bit value at that time is reflected at the start of counting.
Page 446 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT)  Output interrupt  Perform buffer operation. When the control is changed from 0% or 100% duty setting to compare match, the output value of GTIOCA pin at cycle end is determined by GTIOR.GTIOA[3:2] and GTUDDTYC.OADTYR.
Page 447: Hardware Count Start/Count Stop And Clear Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register bbbb aaaa 0000 0000h Time Register write Register write Register write GTUDDTYC.OADTY GTIOC0A pin output GTIOC0B pin output 100% [Setting examples]...
Page 448: Hardware Stop Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.47, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register.
Page 449 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.49, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register.
Page 450 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Count started on the rising Count stopped on the falling edge of GTETRGA edge of GTETRGA GTCNT counter value GTPR register Count started on the rising edge of GTETRGA...
Page 451: Hardware Clear Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.51, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register.
Page 452 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GTCNT counter value Count stopped/cleared at ELC event input Clear by software (by writing 1 to corresponding channel number bit of GTCLR register) Count started at Count started at...
Page 453 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.53 Figure 23.54, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register.
Page 454: Synchronized Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GTCNT counter value Counter cleared Clear by software (by at overflow writing 1 to corresponding channel number bit of GTPR register GTCLR register) Counter cleared by...
Page 455 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register 0000 0000h Time GPT321.GTCNT counter value GPT321.GTPR register 0000 0000h Time GPT322.GTCNT counter value GPT322.GTPR register 0000 0000h Time...
Page 456: Synchronized Operation By Hardware
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register Set initial value cccc bbbb aaaa 0000 0000h Time GPT321.GTCNT counter value GPT321.GTPR register cccc Set initial value bbbb...
Page 457 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register 0000 0000h Time GPT321.GTCNT counter value GPT321.GTPR register 0000 0000h Time GPT322.GTCNT counter value GPT322.GTPR register 0000 0000h Time...
Page 458: Pwm Output Operation Examples
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 23.59, 000b (saw-wave PWM mode) is set. Set count direction Select the count direction (up or down) with the GTUDDTYC register.
Page 459 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter GPT320.GTPR register GPT320.GTCCRB register GPT320.GTCCRA register GPT321.GTCNT counter GPT321.GTPR register GPT321.GTCCRB register GPT321.GTCCRA register GPT322.GTCNT counter GPT322.GTPR register GPT322.GTCCRB register GPT322.GTCCRA register...
Page 460 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter GPT320.GTPR register GPT320.GTCCRA register = GPT320.GTCCRB register GPT321.GTCNT counter GPT321.GTPR register GPT321.GTCCRA register = GPT321.GTCCRB register GPT322.GTCNT counter GPT322.GTPR register GPT322.GTCCRA register...
Page 461 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter GPT320.GTPR register GPT320.GTCCRD register GPT320.GTCCRC register GPT321.GTCNT counter GPT321.GTPR register GPT321.GTCCRD register GPT321.GTCCRC register GPT322.GTCNT counter GPT322.GTPR register GPT322.GTCCRD register GPT322.GTCCRC register...
Page 462 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter GPT320.GTPR register GPT320.GTCCRA register GPT320.GTCCRB register GPT321.GTCNT counter GPT321.GTPR register GPT321.GTCCRA register GPT321.GTCCRB register GPT322.GTCNT counter GPT322.GTPR register GPT322.GTCCRA register GPT322.GTCCRB register...
Page 463 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter GPT320. GTPR register GPT320.GTCCRA register GPT321.GTCNT counter GPT321. GTPR register GPT321.GTCCRA register GPT322.GTCNT counter GPT322. GTPR register GPT322.GTCCRA register GPT320.GTDVU...
Page 464: Phase Counting Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter GPT320. GTPR register GPT320.GTCCRC register GPT320.GTCCRD register GPT321.GTCNT counter GPT321. GTPR register GPT321.GTCCRC register GPT321.GTCCRD register GPT322.GTCNT counter GPT322.
Page 465 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GTIOCA pin input GTIOCB pin input GTCNT counter Up-counting Down-counting Time Figure 23.67 Example of phase counting mode 1 Table 23.7 Conditions of up-counting/down-counting in phase counting mode 1 GTIOCA pin input...
Page 466 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Table 23.8 Conditions of up-counting/down-counting in phase counting mode 2 (A) GTIOCA pin input GTIOCB pin input Operation Register setting High Don’t care...
Page 467 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GTIOCA pin input GTIOCB pin input GTCNT counter Up-counting Down-counting Time Figure 23.70 Example of phase counting mode 2 (C) Table 23.10 Conditions of up-counting/down-counting in phase counting mode 2 (C) GTIOCA pin input...
Page 468 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Table 23.11 Conditions of up-counting/down-counting in phase counting mode 3 (A) GTIOCA pin input GTIOCB pin input Operation Register setting High Don’t care...
Page 469 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GTIOCA pin input GTIOCB pin input GTCNT counter Up-counting Down-counting Time Figure 23.73 Example of phase counting mode 3 (C) Table 23.13 Conditions of up-counting/down-counting in phase counting mode 3 (C) GTIOCA pin input...
Page 470 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Table 23.14 Conditions of up-counting/down-counting in phase counting mode 4 GTIOCA pin input GTIOCB pin input Operation Register setting High Up-counting GTUPSR = 0000 6000h...
Page 471: Output Phase Switching (Gpt_Ops)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GTIOCA pin input GTIOCB pin input GTCNT Up-counting Time Figure 23.76 Example of phase counting mode 5 (B) Table 23.16 Conditions of up-counting/down-counting in phase counting mode 5 (B) GTIOCA pin input...
Page 472 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Soft setting (UF/VF/WF) OPSCR. Hall sensor UF/VF/WF input edge sample GPT_UVWEDGE PCLKD (every PCLKD) sample Input phase (Input U-phase) PWM edge (Input V-phase) sample...
Page 473 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320 PWM Input sel after “U-phase” GTIU Input sel after “V-phase” GTIV Input sel after “W-phase” GTIW Output “U-phase (Up)” GTOUUP Output “U-phase (Lo)”...
Page 474: Input Selection And Synchronization Of External Input Signal
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320 PWM "U-phase" after input selection GTIU "V-phase" after input selection GTIV "W-phase" after input selection GTIW Output enable OPSCR.EN Auto clear Setting by software...
Page 475: Input Sampling
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Table 23.17 Input selection processing method OPSCR register Selection of input phase sampling method Synchronization input/output selection FB bit ALIGN bit (U/V/W-phase) process (GPT_OPS internal node name)
Page 476 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Table 23.19 Output selection control method (positive phase) Enable-phase output Positive-phase output Invert-phase output Output port name (positive phase = up) control (P) control control...
Page 477: Output Selection Control (Group Output Disable Function)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) 23.3.11.5 Output selection control (group output disable function) When OPSCR.GODF is 1 and the signal value selected by the OPSCR.GRP[1:0] bit is high (output disable request), the GPT_OPS output pins are changed to Hi-Z asynchronously and the OPSCR.EN bit is set to 0 by the output disable request signal synchronized with PCLKD.
Page 478: Gpt_Ops Start Operation Setting Flow
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) 23.3.11.7 GPT_OPS start operation setting flow GPT320 operation mode setting GPT320.GTIOCA set the PWM output operation mode of the saw-wave or triangle-wave. For details, see section 23.3.3, PWM Output Operating Mode.
Page 479 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Table 23.21 Interrupt sources (1 of 2) DMAC/DTC Channel Name Interrupt source Interrupt flag activation GPT0_CCMPA GPT320.GTCCRA input capture/compare match TCFA Possible GPT0_CCMPB...
Page 480 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Table 23.21 Interrupt sources (2 of 2) DMAC/DTC Channel Name Interrupt source Interrupt flag activation GPT5_CCMPA GPT165.GTCCRA input capture/compare match TCFA Possible GPT5_CCMPB...
Page 481 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT)  GTCR.MD[2:0] = 001b (saw-wave one-shot pulse mode)  GTCR.MD[2:0] = 110b (triangle-wave PWM mode 3)  GTBER.CCRA[1:0] = 10b, 11b (buffer operation with the GTCCRD register). (5) GPTn_CMPE interrupt (n = 0 to 5, 8) An interrupt request is generated under the following condition: ...
Page 482: Dmac/Dtc Activation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Table 23.22 Interrupt signals and interrupt status flags (2 of 2) Interrupt signal Interrupt status flag GPTn_CCMPA GTST[0] (TCFA) Note: n = 0 to 5, 8 23.4.2...
Page 483: Protection Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) Sampling clock Noise filter enable/ disable register Eliminated pulse Input capture input pin or external trigger input pin Matching three times Signal conveyed...
Page 484: Gtioc Pin Output Negate Control
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register 0000 0000h Time Register write timing is too late Register write Register write for buffer transfer timing bbbb cccc...
Page 485: Initialization Method Of Output Pins
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) end of cycle, GTIOR.OADF[1:0] should be set to 00b (for GTIOCA pin) or GTIOR.OBDF[1:0] should be set to 00b (for GTIOCB pin).
Page 486: Pin Initialization Due To Error During Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register GPT320.GTCCRA register GPT320.GTCCRB register 0000 0000h Time Hi-Z GTIOC0A pin output Hi-Z GTIOC0B pin output Reset is released.
Page 487: Setting Range For Gtcnt Counter
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) GTCCRA > GTPR, no compare match occurs. Similarly, GTCCRB should be set within the range of 0 < GTCCRB < GTPR. If GTCCRB = 0 or GTCCRB = GTPR is set, a compare match occurs within the cycle only when GTCCRB = 0 or GTCCRB = GTPR is satisfied.
Page 488 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 23. General PWM Timer (GPT) If up-counting and down-counting by hardware sources occur at the same time, the GTCNT counter value does not change.
Page 489: Asynchronous General Purpose Timer (Agt)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Asynchronous General Purpose Timer (AGT) 24.1 Overview The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse output, external pulse width or period measurement, and counting external events.
Page 490 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Data bus 16-bit 16-bit 16-bit reload reload reload register register register TCMEA or TCMEB = 1 TCK[2:0] AGT underflows TCK[2:0] = 000b...
Page 491: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) 24.2 Register Descriptions 24.2.1 AGT Counter Register (AGT) Address(es): AGT0.AGT 4008 4000h, AGT1.AGT 4008 4100h Value after reset: Description Setting Range *1, *2...
Page 492: Agt Compare Match B Register (Agtcmb)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) 24.2.3 AGT Compare Match B Register (AGTCMB) Address(es): AGT0.AGTCMB 4008 4004h, AGT1.AGTCMB 4008 4104h Value after reset: Description Setting range b15 to b0...
Page 493 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) TCSTF flag (AGT count status flag) [Setting condition]  When 1 is written to the TSTART bit (the TCSTF flag is set to 1 in synchronization with the count source). [Clearing conditions] ...
Page 494: Agt Mode Register 1 (Agtmr1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) 24.2.5 AGT Mode Register 1 (AGTMR1) Address(es): AGT0.AGTMR1 4008 4009h, AGT1.AGTMR1 4008 4109h TEDGP — TCK[2:0] TMOD[2:0] Value after reset: Symbol Bit name...
Page 495: Agt Mode Register 2 (Agtmr2)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) 24.2.6 AGT Mode Register 2 (AGTMR2) Address(es): AGT0.AGTMR2 4008 400Ah, AGT1.AGTMR2 4008 410Ah — — — — CKS[2:0] Value after reset: Symbol...
Page 496: Agt Event Pin Select Register (Agtisr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Symbol Bit name Description — Reserved This bit is read as 0. The write value should be 0. AGTOn output enable 0: AGTOn output disabled 1: AGTOn output enabled.
Page 497: Agt Compare Match Function Select Register (Agtcmsr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) 24.2.9 AGT Compare Match Function Select Register (AGTCMSR) Address(es): AGT0.AGTCMSR 4008 400Eh, AGT1.AGTCMSR 4008 410Eh TOPOL — TOEB TCMEB —...
Page 498: Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) SEL[1:0] bits (AGTIOn Pin Select) The SEL[1:0] bits select the AGTIOn pin function. TIES (AGTIOn Input Enable) The TIES bit enables or disables an external event input.
Page 499: Reload Register And Compare Register A/B Rewrite Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Write 1 to TSTART bit in AGTCR register with software Write 1234h to AGT register with software Write 5678h to AGT register with software Register write clock Count source...
Page 500: Timer Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Write 1 to TSTART bit in AGTCR register with software Write 2345h to AGTCMA register with software Write 1234h to AGTCMA register with software Register write clock Count source...
Page 501: Pulse Output Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Count source Previous value Reload register New value (1010h) (0300h) Counter reloading occurs AGT counter 02FAh 02F9h 02F8h 02F7h 1010h 100Fh 100Eh ••••• •••••...
Page 502: Event Counter Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Write 1 to TSTART bit in AGTCR register with software Write 0002h to Write 0004h to AGT register with AGT register with software software...
Page 503: Pulse Width Measurement Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Event counter mode is entered TMOD[2:0] bits in 010b AGTMR1 register Event is counted at rising edge AGTIOC register TSTART bit in AGTCR register...
Page 504: Pulse Period Measurement Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) ends, the counter is stopped, the TEDGF bit in the AGTCR register is set to 1 (active edge received), and an interrupt request is generated.
Page 505: Compare Match Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Count source TSTART bit in AGTCR register Measurement pulse input Counter is reloaded AGT counter 0300h •••• 02FFh 02FEh 0300h 02FFh 02FEh 02FDh02FCh 02FBh 02FAh 02F9h 02F8h 02F7h 0300h 02FFh...
Page 506 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) n = AGT register content m = Compare Match A register setting value p = Compare Match B register setting value FFFFh Count starts Underflow...
Page 507: Output Settings For Each Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) 24.3.9 Output Settings for each Mode Table 24.5 Table 24.7 list the states of pins AGTOn, AGTIOn, and AGTOB0 in each mode. Table 24.5 AGTOn pin setting AGTIOC register...
Page 508: Interrupt Sources
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) Table 24.8 Usable setting in Software Standby mode (AGT0) Operating mode AGTMR1.TCK[2:0] Operating clock Resurgence factor of CPU Timer mode 100b or 110b AGTLCLK or AGTSCLK –...
Page 509: Access To Counter Register
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT) bit in the AGTCR register remains 0 (count stops) for 3 cycles of the count source. Do not access the registers associated with AGT other than the TCSTF bit until this bit is set to 1 (count in progress).
Page 510: When Count Is Forcibly Stopped By Tstop Bit
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 24. Asynchronous General Purpose Timer (AGT)  In pulse period measurement mode, input pulse period is expressed mathematically as follows: Period of input pulse = (initial value of counter [AGT register] - reading value of the read-out buffer) + 1 24.4.6 When Count is Forcibly Stopped by TSTOP Bit After the counter is forcibly stopped by the TSTOP bit in the AGTCR register, do not access the following I/O registers...
Page 511: Realtime Clock (Rtc)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) Realtime Clock (RTC) 25.1 Overview The RTC has two counting modes, calendar count mode and binary count mode, that are used by switching register settings.
Page 512 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) Internal peripheral bus Realtime clock (RTC) Bus interface To each RCR2 RTCOUT function Time counter 1-Hz/64-Hz output Alarm function prescaler XCIN 128 Hz...
Page 513: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) 25.2 Register Descriptions Write or read from the RTC registers as described in section 25.6.5, Notes on Writing to and Reading from Registers.
Page 514: Minute Counter (Rmincnt)/Binary Counter 1 (Bcnt1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) Symbol Bit name Description — Reserved Set this bit to 0. It is read as the set value. The RSECCNT counter sets and counts the BCD-coded second value. It counts the carries generated once per second in the 64-Hz counter.
Page 515: Hour Counter (Rhrcnt)/Binary Counter 2 (Bcnt2)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) (2) In binary count mode: Address(es): RTC.BCNT1 4004 4004h BCNT[15:8] Value after reset: x: Undefined BCNT1 is a read/write 32-bit binary counter b15 to b8 that performs count operation by a carry generated for each second of the 64-Hz counter.
Page 516: Day-Of-Week Counter (Rwkcnt)/Binary Counter 3 (Bcnt3)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) bit in RCR2. To read this counter, follow the procedure in section 25.3.5, Reading 64-Hz Counter and Time. 25.2.5 Day-of-Week Counter (RWKCNT)/Binary Counter 3 (BCNT3) (1) In calendar count mode:...
Page 517: Day Counter (Rdaycnt)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) 25.2.6 Day Counter (RDAYCNT) Address(es): RTC.RDAYCNT 4004 400Ah — — DATE10[1:0] DATE1[3:0] Value after reset: x: Undefined Symbol Bit name Description b3 to b0 DATE1[3:0]...
Page 518: Year Counter (Ryrcnt)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) 25.2.8 Year Counter (RYRCNT) Address(es): RTC.RYRCNT 4004 400Eh — — — — — — — — YR10[3:0] YR1[3:0] Value after reset: x: Undefined Symbol Bit name...
Page 519: Minute Alarm Register (Rminar)/Binary Counter 1 Alarm Register (Bcnt1Ar)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC)  RYRAREN. When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. The RSECAR values from 00 through 59 (in BCD) can be specified.
Page 520: Hour Alarm Register (Rhrar)/Binary Counter 2 Alarm Register (Bcnt2Ar)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) (2) In binary count mode: Address(es): RTC.BCNT1AR 4004 4012h BCNTAR[15:8] Value after reset: x: Undefined BCNT1AR is a read/write alarm register associated with the 32-bit binary counter from b15 to b8. This register is set to 00h by an RTC software reset.
Page 521: Day-Of-Week Alarm Register (Rwkar)/Binary Counter 3 Alarm Register (Bcnt3Ar)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) RTC software reset. (2) In binary count mode: Address(es): RTC.BCNT2AR 4004 4014h BCNTAR[23:16] Value after reset: x: Undefined BCNT2AR is a read/write alarm register associated with the 32-bit binary counter b23 to b16. This register is cleared to 00h by an RTC software reset.
Page 522: Date Alarm Register (Rdayar)/Binary Counter 0 Alarm Enable Register (Bcnt0Aer)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) correctly. This register is set to 00h by an RTC software reset. (2) In binary count mode: Address(es): RTC.BCNT3AR 4004 4016h BCNTAR[31:24] Value after reset: x: Undefined...
Page 523: Month Alarm Register (Rmonar)/Binary Counter 1 Alarm Enable Register (Bcnt1Aer)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) (2) In binary count mode: Address(es): RTC.BCNT0AER 4004 4018h ENB[7:0] Value after reset: x: Undefined BCNT0AER is a read/write register to set the alarm enable associated with the 32-bit binary counter b7 to b0. The binary counter (BCNT[31:0]) associated with the ENB[31:0] bits that are set to 1 is compared with the binary alarm register (BCNTAR[31:0]), and when all match, the IR flag associated with the RTC_ALM interrupt becomes 1.
Page 524: Year Alarm Register (Ryrar)/Binary Counter 2 Alarm Enable Register (Bcnt2Aer)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) (2) In binary count mode: Address(es): RTC.BCNT1AER 4004 401Ah ENB[15:8] Value after reset: x: Undefined BCNT1AER is a read/write register for setting the alarm enable associated with the 32-bit binary counter b15 to b8. The binary counter (BCNT[31:0]) associated with the ENB[31:0] bits that are set to 1 is compared with the binary alarm register (BCNTAR[31:0]), and when all match, the IR flag associated with the RTC_ALM interrupt becomes 1.
Page 525: Year Alarm Enable Register (Ryraren)/Binary Counter 3 Alarm Enable Register (Bcnt3Aer)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) 25.2.16 Year Alarm Enable Register (RYRAREN)/Binary Counter 3 Alarm Enable Register (BCNT3AER) (1) In calendar count mode: Address(es): RTC.RYRAREN 4004 401Eh —...
Page 526: Rtc Control Register 1 (Rcr1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) 25.2.17 RTC Control Register 1 (RCR1) Address(es): RTC.RCR1 4004 4022h PES[3:0] RTCOS Value after reset: x: Undefined Symbol Bit name Description Alarm Interrupt Enable 0: An alarm interrupt request is disabled...
Page 527: Rtc Control Register 2 (Rcr2)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) 25.2.18 RTC Control Register 2 (RCR2) (1) In calendar count mode: Address(es): RTC.RCR2 4004 4024h CNTM HR24 AADJP AADJE RTCOE ADJ30 RESET START Value after reset: x: Undefined Symbol...
Page 528 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) ADJ30 (30-Second Adjustment) The ADJ30 bit is for 30-second adjustment. When 1 is written to the ADJ30 bit, the RSECCNT value of 30 seconds or less is rounded down to 00 second and the value of 30 seconds or more is rounded up to 1 minute.
Page 529 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) (2) In binary count mode: Address(es): RTC.RCR2 4004 4024h CNTM — AADJP AADJE RTCOE — RESET START Value after reset: x: Undefined Symbol Bit name...
Page 530: Rtc Control Register 4 (Rcr4)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) AADJE (Automatic Adjustment Enable) The AADJE bit controls (enables or disables) automatic adjustment. Set the plus-minus bits (RADJ.PMADJ[1:0]) to 00b (adjustment is not performed) before changing the value of the AADJE bit.
Page 531: Frequency Register (Rfrh/Rfrl)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) 25.2.20 Frequency Register (RFRH/RFRL) Address(es): RTC.RFRH 4004 402Ah — — — — — — — — — — — —...
Page 532: Time Error Adjustment Register (Radj)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) 25.2.21 Time Error Adjustment Register (RADJ) Address(es): RTC.RADJ 4004 402Eh PMADJ[1:0] ADJ[5:0] Value after reset: x: Undefined Symbol Bit name Description b5 to b0 ADJ[5:0]...
Page 533 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) Symbol Bit name Description b5, b4 TCNF[1:0] Time Capture Noise b5 b4 0 0: Noise filter is off Filter Control 0 1: Setting prohibited 1 0: Noise filter is on (count source) 1 1: Noise filter is on (count source by divided by 32).
Page 534: Second Capture Register 0 (Rseccp0) /Bcnt0 Capture Register 0
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) 25.2.23 Second Capture Register 0 (RSECCP0) /BCNT0 Capture Register 0 (BCNT0CP0) (1) In calendar count mode: Address(es): RTC.RSECCP0 4004 4052h —...
Page 535: Hour Capture Register 0 (Rhrcp0) /Bcnt2 Capture Register 0 (Bcnt2Cp0)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) Symbol Bit name Description — Reserved This bit is read as 0 after an RTC software reset RMINCP0 is a read-only register that captures the RMINCNT value when a time capture event is detected. The event detection time detected by the RTCIC0 pin is stored in the RMINCP0 register.
Page 536: Date Capture Register 0 (Rdaycp0) /Bcnt3 Capture Register 0 (Bcnt3Cp0)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) (2) In binary count mode: Address(es): RTC.BCNT2CP0 4004 4056h BCNTCP0[23:16] Value after reset: x: Undefined BCNT2CP0 is a read-only register that captures the BCNT2 value when a time capture event is detected. The event detection time detected by the RTCIC0 pin is stored in the BCNT2CP0 register.
Page 537: Month Capture Register 0 (Rmoncp0)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) 25.2.27 Month Capture Register 0 (RMONCP0) (1) In calendar count mode: Address(es): RTC.RMONCP0 4004 405Ch — — — MON10 MON1[3:0] Value after reset: x: Undefined...
Page 538: Setting The Time
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) Select the count source RCR4.RCKSEL bit setting Supply 6 clocks of the clock selected by the Supply 6 clocks of the count source RCR4.RCKSEL bit Set the START bit to 0 Wait for the RCR2.START bit to become 0...
Page 539: 30-Second Adjustment
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) Set the START bit to 0 Write 0 to the RCR2.START bit START = 0 Wait for the RCR2.START bit to become 0 Execute an RTC software reset Write 1 to the RCR2.RESET bit RESET = 0...
Page 540: Reading 64-Hz Counter And Time
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) 25.3.5 Reading 64-Hz Counter and Time Figure 25.6 shows how to read a 64-Hz counter and time. (a) To read the time without using interrupt Disable the NVIC carry interrupt request Write 1 to the Interrupt Clear-Enable Register corresponding to the RTC_CUP interrupt...
Page 541: Alarm Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) 25.3.6 Alarm Function Figure 25.7 shows how to use the alarm function. Write 1 to the Interrupt Clear-Enable Register Disable the NVIC alarm interrupt request corresponding to the RTC_ALM interrupt Set alarm enable at the same time as or after the...
Page 542: Time Error Adjustment Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) Enable the alarm interrupt The RCR1.AIE bit register is set to 1 Write 0 to the Interrupt Clear-Enable Register Disable the alarm interrupt request of associated with the RTC_ALM interrupt the NVIC...
Page 543: Adjustment By Software
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) (2) Example 2: Sub-clock oscillator running at 32.766 kHz (a) Adjustment procedure When the sub-clock oscillator is running at 32.766 kHz, 1 second elapses every 32,766 clock cycles. The RTC is meant to run at 32,768 clock cycles, so the clock runs slow by 2 clock cycles every second.
Page 544: Procedure For Stopping Adjustment
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) To change automatic adjustment to adjustment by software: 1. Set the RADJ.PMADJ[1:0] bits to 00b (adjustment is not performed). 2.
Page 545: Interrupt Sources
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) Count source RTCIC0 Internal event-input signal Since the level has matched three Since the level has only matched times, it is conveyed to the internal twice, it is not conveyed to the circuits.
Page 546: Event Link Output
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) Sequence for setting the alarm Wait until the alarm Alarm register settings time setting is in progress confirmed Alarm registers Clock counters Match while settings are being made Interrupt flag...
Page 547: Interrupt Handling And Event Linking
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) The event generation period immediately after the event generation is selected, is not guaranteed. Note: If event linking from the RTC is used, only set the ELC after setting the RTC, for example, initialization and time settings.
Page 548: Rtcout (1-Hz/64-Hz) Clock Output
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) Set the RCR1.PES[3:0] bits and Set the period and enable interrupt requests write 1 to the RCR1.PIE bit The period is not guaranteed Confirm generation of the first periodic interrupt*...
Page 549: When Switching Source Clock
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 25. Realtime Clock (RTC) Alternatively, when the sub-clock oscillator is not used as the system clock or realtime clock, the counter can be stopped by writing 0 (sub-clock oscillator is selected) to the RCR4.RCKSEL bit and stopping the sub-clock oscillator.
Page 550: Watchdog Timer (Wdt)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 26. Watchdog Timer (WDT) Watchdog Timer (WDT) 26.1 Overview The Watchdog Timer (WDT) is a 14-bit down-counter and can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT.
Page 551: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 26. Watchdog Timer (WDT) Interrupt request (WDT_NMIUNDF) Interrupt control circuit WDT output Reset control circuit Clock frequency divider PCLKB/4 PCLKB/64 PCLKB PCLKB/128 WDT control circuit 14-bit down-counter PCLKB/512 PCLKB/2048...
Page 552: Wdt Control Register (Wdtcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 26. Watchdog Timer (WDT) 26.2.2 WDT Control Register (WDTCR) Address(es): WDT.WDTCR 4004 4202h — — RPSS[1:0] — — RPES[1:0] CKS[3:0] — — TOPS[1:0] Value after reset: Symbol Bit name...
Page 553 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 26. Watchdog Timer (WDT) Table 26.2 Timeout period settings CKS[3:0] bits TOPS[1:0] bits Timeout period Clock division ratio (number of cycles) PCLKB clock cycles PCLKB/4 1024 4096...
Page 554: Wdt Status Register (Wdtsr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 26. Watchdog Timer (WDT) Table 26.3 Relationship between timeout period and window start and end counter values Timeout period Window start and end counter value TOPS[1:0] bits Cycles Counter value...
Page 555: Wdt Reset Control Register (Wdtrcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 26. Watchdog Timer (WDT) CNTVAL[13:0] bits (Down-Counter Value) Read the CNTVAL[13:0] bits to confirm the value of the down-counter. The read value might differ from the actual count by a value of one count.
Page 556: Wdt Count Stop Control Register (Wdtcstpr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 26. Watchdog Timer (WDT) 26.2.5 WDT Count Stop Control Register (WDTCSTPR) Address(es): WDT.WDTCSTPR 4004 4208h SLCST — — — — — — — Value after reset: Symbol Bit name...
Page 557 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 26. Watchdog Timer (WDT) After the reset state is released, set the following to Sleep mode in the WDTCSTPR register:  Clock division ratio ...
Page 558: Auto Start Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 26. Watchdog Timer (WDT) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period RES pin Control register (WDTCR) (1) Initial value (2) Set value Writing to the Writing to the...
Page 559: Controlling Writes To The Wdtcr, Wdtrcr, And Wdtcstpr Registers
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 26. Watchdog Timer (WDT) However, if the down-counter underflows because refreshing of the down-counter is not possible due to a runaway program or if a refresh error occurs due to refreshing outside the refresh-permitted period, the WDT outputs a reset signal or non-maskable interrupt request/interrupt request (WDT_NMIUNDF).
Page 560: Refresh Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 26. Watchdog Timer (WDT) becomes 1 to protect WDTCR, WDTRCR and WDTCSTPR against subsequent write attempts. This protection is released by a reset source of the WDT. With other reset sources, the protection is not released. Figure 26.5 shows control waveforms produced in response to writing to the WDTCR.
Page 561: Reset Output
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 26. Watchdog Timer (WDT) Peripheral clock (PCLKB) Data written to WDTRR register WDTRR register Valid write signal (internal signal) WDTRR register Invalid Refresh synchronization signal Refresh signal...
Page 562: Associations Between Option Function Select Register 0 (Ofs0) And Wdt Registers
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 26. Watchdog Timer (WDT) Peripheral clock (PCLKB) Refreshing (n)h (n-1)h Counter value (n+1)h (n-1)h 0FFFh Bits WDTSR.CNTVAL (n)h (n+1)h (n-1)h (n-1)h 0FFFh [13:0] WDTSR.CNTVAL [13:0] read signal (internal signal)
Page 563: Independent Watchdog Timer (Iwdt)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 27. Independent Watchdog Timer (IWDT) Independent Watchdog Timer (IWDT) 27.1 Overview The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be serviced periodically to prevent counter underflow.
Page 564: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 27. Independent Watchdog Timer (IWDT) Interrupt request (IWDT_NMIUNDF) Interrupt control circuit IWDT reset output Reset control circuit Clock frequency divider IWDTCLK IWDTCLK IWDTCLK/16 IWDTCLK/32 IWDT control circuit 14-bit counter...
Page 565: Iwdt Status Register (Iwdtsr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 27. Independent Watchdog Timer (IWDT) 27.2.2 IWDT Status Register (IWDTSR) Address(es): IWDT.IWDTSR 4004 4404h REFEF UNDFF CNTVAL[13:0] Value after reset: Symbol Bit name Description b13 to b0 CNTVAL[13:0]...
Page 566: Option Function Select Register 0 (Ofs0)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 27. Independent Watchdog Timer (IWDT) 27.2.3 Option Function Select Register 0 (OFS0) For information on the Option Function Select Register 0 (OFS0), see section 7.2.1, Option Function Select Register 0 (OFS0).
Page 567 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 27. Independent Watchdog Timer (IWDT) value smaller than the window start position. If the window end position is greater than the window start position, only the window start position setting is enabled.
Page 568: Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 27. Independent Watchdog Timer (IWDT) 27.3 Operation 27.3.1 Auto Start Mode When the IWDT Start Mode Select bit (OFS0.IWDTSTRT) in the Option Function Select Register 0 is 0, auto start mode is selected, otherwise IWDT is disabled.
Page 569: Refresh Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 27. Independent Watchdog Timer (IWDT) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period RES pin Refresh the counter Active: High Counting starts Counting starts Counting starts...
Page 570: Status Flags
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 27. Independent Watchdog Timer (IWDT) After FFh is written to the IWDTRR register, refreshing the counter requires up to 4 cycles of the signal for counting (the IWDT-dedicated clock frequency division ratio select bits (OFS0.IWDTCKS[3:0]) determine how many cycles of the IWDT-dedicated clock (IWDTCLK) make up 1 cycle for counting).
Page 571: Reset Output
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 27. Independent Watchdog Timer (IWDT) 27.3.4 Reset Output When the IWDT Reset Interrupt Request Select bit (OFS0.IWDTRSTIRQS) in the Option Function Select Register 0 (OFS0) is set to 1, a reset signal is output when an underflow in the counter or a refresh error occurs.
Page 572: Usage Notes
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 27. Independent Watchdog Timer (IWDT) 27.5 Usage Notes 27.5.1 Refresh Operations While configuring the refresh time, consider variations in the range of errors given the accuracy of PCLKB and IWDTCLK.
Page 573: Usb 2.0 Full-Speed Module (Usbfs)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) USB 2.0 Full-Speed Module (USBFS) 28.1 Overview The MCU provides a USB 2.0 Full-Speed module (USBFS) that operates as a host or device controller compliant with the Universal Serial Bus (USB) specification revision 2.0.
Page 574 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Figure 28.1 shows a block diagram of the USBFS. Battery charging control controller LINK core Registers Registers USB device controller USB_DP...
Page 575: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2 Register Descriptions 28.2.1 System Configuration Control Register (SYSCFG) Address(es): USBFS.SYSCFG 4009 0000h DCFM DRPD DPRPU DMRP —...
Page 576: System Configuration Status Register 0 (Syssts0)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) DMRPU (D- Line Resistor Control* The DMRPU bit enables or disables pulling up the D- line in device controller mode. When the DMRPU bit is set to 1 in device controller mode, the USBFS pulls up the D- line to notify the USB host that it attached as a low-speed device.
Page 577: Device State Control Register 0 (Dvstctr0)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Symbol Bit name Description b15, b14 OVCMON[1:0] External USB_OVRCURA/ OVCMON[1] bit indicates the USB_OVRCURA pin status USB_OVRCURB Input Pin OVCMON[0] bit indicates the USB_OVRCURB pin status.
Page 578 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Symbol Bit name Description USBRST USB Bus Reset Output 0: USB bus reset signal not output 1: USB bus reset signal output. RWUPE Wakeup Detection Enable 0: Downstream port wakeup disabled...
Page 579: Cfifo Port Register (Cfifo/Cfifol)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Always set this bit to 0 in device controller mode. RWUPE (Wakeup Detection Enable) The RWUPE bit enables or disables remote wakeup signals (resume signals) from downstream peripheral devices in host controller mode.
Page 580 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS)  D1FIFO. Each FIFO port is configured with:  A port register (CFIFO, D0FIFO, or D1FIFO) that handles reading of data from the FIFO buffer and writing of data to the FIFO buffer ...
Page 581: Cfifo Port Select Register (Cfifosel)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.5 CFIFO Port Select Register (CFIFOSEL) D0FIFO Port Select Register (D0FIFOSEL) D1FIFO Port Select Register (D1FIFOSEL) CFIFOSEL Address(es): USBFS.CFIFOSEL 4009 0020h BIGEN...
Page 582 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) During FIFO buffer access, the current pipe specification is maintained until the access is complete, even if software attempts to change the CURPIPE[3:0] setting.
Page 583 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Symbol Bit name Description FIFO Port Access Bit Width 0: 8-bit width 1: 16-bit width. — Reserved This bit is read as 0.
Page 584: Cfifo Port Control Register (Cfifoctr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) (Buffer Pointer Rewind) The REW bit specifies whether to rewind the buffer pointer. When the selected pipe is receiving, setting this bit to 1 while the FIFO buffer is being read allows re-reading of the FIFO buffer from the first data.
Page 585: Interrupt Enable Register 0 (Intenb0)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) The USBFS sets these bits to 0 when all the data is read from one FIFO buffer plane. In double buffer mode, if data is received in one FIFO buffer plane before all the data is read from the other plane, the USBFS sets these bits to indicate the length of the received data in the former plane when all of the data is read from the latter plane.
Page 586: Interrupt Enable Register 1 (Intenb1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Symbol Bit name Description BRDYE Buffer Ready Interrupt Enable 0: Interrupt output disabled 1: Interrupt output enabled. NRDYE Buffer Not Ready Response Interrupt Enable 0: Interrupt output disabled...
Page 587: Brdy Interrupt Enable Register (Brdyenb)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Symbol Bit name Description OVRCRE Overcurrent Input Change Interrupt 0: Interrupt output disabled Enable 1: Interrupt output enabled. Note: The bits in INTENB1 can only be set to 1 in host controller mode.
Page 588: Nrdy Interrupt Enable Register (Nrdyenb)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.10 NRDY Interrupt Enable Register (NRDYENB) Address(es): USBFS.NRDYENB 4009 0038h PIPE9N PIPE8N PIPE7N PIPE6N PIPE5N PIPE4N PIPE3N PIPE2N PIPE1N PIPE0N...
Page 589: Sof Output Configuration Register (Sofcfg)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Symbol Bit name Description PIPE1BEMPE BEMP Interrupt Enable for Pipe 1 0: Interrupt output disabled 1: Interrupt output enabled. PIPE2BEMPE BEMP Interrupt Enable for Pipe 2 0: Interrupt output disabled...
Page 590: Interrupt Status Register 0 (Intsts0)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) EDGESTS (Edge Interrupt Output Status Monitor) The EDGESTS bit indicates 1 during the edge processing of an edge interrupt output signal. Confirm that this bit is 0 before stopping the clock supply to the USBFS.
Page 591 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Symbol Bit name Description VBINT VBUS Interrupt Status 0: VBUS interrupts are not generated R/W* 1: VBUS interrupts are generated. x: Don’t care Note 1.
Page 592: Interrupt Status Register 1 (Intsts1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) DVST (Device State Transition Interrupt Status) In device controller mode, the USBFS updates the value of the DVSQ[2:0] bits and sets the DVST bit to 1 when detecting a change in the device state.
Page 593 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Symbol Bit name Description BCHG USB Bus Change Interrupt Status* 0: BCHG interrupts are not generated 1: BCHG interrupts are generated. OVRCR Overcurrent Input Change Interrupt 0: OVRCR interrupts are not generated...
Page 594 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Values read from the EOFERR bit in device controller mode are invalid. ATTCH (ATTCH Interrupt Status) The ATTCH bit indicates the status of USB attach detection interrupts in host controller mode. The USBFS detects the ATTCH interrupt and sets this bit to 1 on detecting a J- or K-state on the full- or low-speed signal level for 2.5 μs.
Page 595: Brdy Interrupt Status Register (Brdysts)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.15 BRDY Interrupt Status Register (BRDYSTS) Address(es): USBFS.BRDYSTS 4009 0046h PIPE9B PIPE8B PIPE7B PIPE6B PIPE5B PIPE4B PIPE3B PIPE2B PIPE1B PIPE0B...
Page 596: Bemp Interrupt Status Register (Bempsts)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Symbol Bit name Description PIPE4NRDY NRDY Interrupt Status for Pipe 4 0: Interrupts are not generated 1: Interrupts are generated. PIPE5NRDY NRDY Interrupt Status for Pipe 5 0: Interrupts are not generated...
Page 597: Frame Number Register (Frmnum)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.18 Frame Number Register (FRMNUM) Address(es): USBFS.FRMNUM 4009 004Ch OVRN CRCE — — — FRNM[10:0] Value after reset: Symbol Bit name Description...
Page 598: Usb Request Type Register (Usbreq)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.19 USB Request Type Register (USBREQ) Address(es): USBFS.USBREQ 4009 0054h BREQUEST[7:0] BMREQUESTTYPE[7:0] Value after reset: Symbol Bit name Description b7 to b0 BMREQUESTTYPE[7:0]...
Page 599: Usb Request Index Register (Usbindx)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Note 1. In device controller mode, these bits are readable, but writing to them has no effect. In host controller mode, these bits are both read/write.
Page 600: Usb Request Length Register (Usbleng)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.22 USB Request Length Register (USBLENG) Address(es): USBFS.USBLENG 4009 005Ah WLENTUH[15:0] Value after reset: Symbol Bit name Description b15 to b0 WLENTUH[15:0]...
Page 601: Dcp Maximum Packet Size Register (Dcpmaxp)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) device controller mode, set the DIR bit to 0. SHTNAK (Pipe Disabled at End of Transfer) The SHTNAK bit specifies whether to change PID to NAK on transfer end when the selected pipe is receiving. It is only valid when the selected pipe is receiving.
Page 602: Dcp Control Register (Dcpctr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) DEVSEL[3:0] bits (Device Select* In host controller mode, the DEVSEL[3:0] bits specify the address of the target peripheral device for a control transfer. Set up the device address in the associated DEVADDn (n = 0 to 5) register first, and then set these bits to the corresponding value.
Page 603 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) a. Write all of the transmit data to the FIFO buffer while the DVSTCTR0.UACT bit is 1 and PID is NAK. b.
Page 604 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) In device controller mode, the USBFS sets the SQMON bit to 1 (specifies DATA1 as the expected value) on successful reception of the setup packet.
Page 605: Pipe Window Select Register (Pipesel)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.26 Pipe Window Select Register (PIPESEL) Address(es): USBFS.PIPESEL 4009 0064h — — — — — — — —...
Page 606: Pipe Configuration Register (Pipecfg)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.27 Pipe Configuration Register (PIPECFG) Address(es): USBFS.PIPECFG 4009 0068h SHTNA TYPE[1:0] — — — BFRE DBLB — —...
Page 607 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) EPNUM[3:0] bits (Endpoint Number* The EPNUM[3:0] bits specify the endpoint number for the selected pipe. Setting 0000b indicates the pipe is not used. Set these bits so that the combination of the DIR and EPNUM[3:0] settings is different from those for other pipes.
Page 608: Pipe Maximum Packet Size Register (Pipemaxp)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.28 Pipe Maximum Packet Size Register (PIPEMAXP) Address(es): USBFS.PIPEMAXP 4009 006Ch DEVSEL[3:0] — — — MXPS[8:0] Value after reset: Symbol Bit name Description...
Page 609: Pipe Cycle Control Register (Pipeperi)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.29 Pipe Cycle Control Register (PIPEPERI) Address(es): USBFS.PIPEPERI 4009 006Eh — — — IFIS — — — —...
Page 610: Pipen Control Registers (Pipenctr) (N = 1 To 9)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.30 PIPEn Control Registers (PIPEnCTR) (n = 1 to 9) PIPEnCTR (n = 1 to 5) Address(es): USBFS.PIPE1CTR 4009 0070h, USBFS.PIPE2CTR 4009...
Page 611 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) The USBFS changes the PIPEnCTR.PID[1:0] setting in the following cases:  The USBFS sets PID to NAK on recognizing completion of the transfer when the selected pipe is receiving and the PIPECFG.SHTNAK bit for the selected pipe is set to 1 by software ...
Page 612 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.8 Operation of the USBFS based on the PID[1:0] setting in device controller mode (2 of 2) Transfer direction PID[1:0] value Transfer type...
Page 613 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.9 Data cleared by the USBFS when ACLRM = 1 (2 of 2) Number Data cleared by setting the ACLRM bit Situations requiring data clear Interval count value when the selected pipe is the isochronous When resetting the interval count value...
Page 614 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.10 BSTS bit operation DIR value BFRE value DCLRM value BSTS bit function Set to 1 when received data can be read from the FIFO buffer, and set to 0 on completion of data read Setting prohibited Set to 1 when received data can be read from the FIFO buffer, and set to 0 when...
Page 615 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) PID[1:0] bits (Response PID) The PID[1:0] bits specify the response type for the next transaction of the selected pipe. The default PID[1:0] setting is NAK.
Page 616: Pipen Transaction Counter Enable Register (Pipentre) (N = 1 To 5)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.11 Data cleared by USBFS when ACLRM = 1 Number Data cleared by setting the ACLRM bit Situations requiring data clear All data in the FIFO buffer allocated to the selected pipe When initializing the selected pipe...
Page 617: Pipen Transaction Counter Register (Pipentrn) (N = 1 To 5)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.32 PIPEn Transaction Counter Register (PIPEnTRN) (n = 1 to 5) Address(es): USBFS.PIPE1TRN 4009 0092h, USBFS.PIPE2TRN 4009 0096h, USBFS.PIPE3TRN 4009 009Ah,...
Page 618: Device Address N Configuration Register (Devaddn) (N = 0 To 5)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.33 Device Address n Configuration Register (DEVADDn) (n = 0 to 5) Address(es): USBFS.DEVADD0 4009 00D0h, USBFS.DEVADD1 4009 00D2h, USBFS.DEVADD2 4009 00D4h,...
Page 619: Bc Control Register 0 (Usbbcctrl0)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.2.35 BC Control Register 0 (USBBCCTRL0) Address(es): USBFS.USBBCCTRL0 4009 00B0h PDDET CHGDE BATCH VDMS IDPSIN VDPSR IDMSIN IDPSR RPDM —...
Page 620: Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) VDMSRCE0 (D- Pin VDMSRC (0.6 V) Output Control) When the VDMSRCE0 bit is set to 1 in device controller mode, output is enabled on secondary detection and VDMSRC (0.6 V) is applied to D-.
Page 621: Example Of Usb External Connection Circuits
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.3.1.4 Example of USB external connection circuits The host recognizes a USB device when one of the data lines is pulled up. The MCU can use switching of the internal pull-up resistor for this.
Page 622 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Figure 28.3 shows an example of host connection of the USB connector. External connection USB_VBUSEN Non-OTG power supply IC for USB USB_OVRCURA...
Page 623 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Figure 28.4 shows an example of functional connection of the USB connector in bus-powered state. External connection Each system power B connector supply (3.3 V)
Page 624 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Figure 28.5 shows an example of functional connection of the USB connector in bus-powered state 2. External connection B connector USB_VBUS VBUS...
Page 625: Interrupt Sources
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Figure 28.6 shows an example of functional connection of the USB connector with Battery Charging Rev 1.2 supported. External connection Charging IC supporting Battery...
Page 626 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.13 Interrupt sources (1 of 2) Applicable Bit to be controller Name Interrupt source function Status flag ...
Page 627 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.13 Interrupt sources (2 of 2) Applicable Bit to be controller Name Interrupt source function Status flag ...
Page 628 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Figure 28.7 shows the circuits related to the USBFS interrupts. USBFS_USBR USB bus reset detected INTENB0 INTSTS0 VBSE Set_Address detected VBINT...
Page 629: Interrupt Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.14 shows the interrupts generated by the USBFS. Table 28.14 USBFS interrupts Interrupt DMAC name Interrupt status flag activation activation Priority...
Page 630 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) interrupt status of the selected pipe can be set to 0 by writing 0 to the associated PIPEnBRDY bit through software. In this case, write 1 to the PIPEnBRDY bits for the other pipes.
Page 631 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Figure 28.8 shows the timing of BRDY interrupt generation. (1) Example of zero-length packet reception or data packet reception when BFRE = 0 (single-buffer mode) Token Packet Data Packet ACK Handshake...
Page 632: Nrdy Interrupt
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.3.3.2 NRDY interrupt On generating an internal NRDY interrupt request for the pipe whose PID bits are set to BUF by software, the USBFS sets the associated PIPEnNRDY bit in NRDYSTS to 1.
Page 633 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) (2) In device controller mode (a) For transmitting pipes  When an IN token is received while there is no data to be transmitted in the FIFO buffer. In this case, the USBFS generates a NRDY interrupt request on reception of the IN token and sets the NRDYSTS.PIPEnNRDY bit to 1.
Page 634: Bemp Interrupt
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) (1) Example of data transmission (single-buffer mode) IN token packet USB bus NAK handshake FIFO buffer status Ready for write access (there is no data to be transmitted) NRDY interrupt (NRDYSTS.PIPEnNRDY bit)
Page 635: Device State Transition Interrupt (Device Controller Mode)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) controller mode. (2) For receiving pipes When a successfully-received data packet size exceeds the specified maximum packet size. In this case, the USBFS generates a BEMP interrupt request, sets the associated BEMPSTS.PIPEnBEMP bit to 1, discards the received data, and changes the associated PID[1:0] setting for the pipe to STALL (11b).
Page 636: Control Transfer Stage Transition Interrupt (Device Controller Mode)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Suspended state detection (DVST is set to 1) Powered Suspended state state (DVSQ = 000b) (DVSQ = 100b) Resume (RESM is set to 1) USB bus reset detection (DVST is set to 1)
Page 637: Frame Update Interrupt
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS)  An IN token is received at the status stage  A data packet with DATAPID = DATA0 is received at the status stage. (2) Control write transfer errors ...
Page 638: Resume Interrupt
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.3.3.8 Resume interrupt In device controller mode, a resume interrupt is generated when the device state is the Suspend state and the USB bus state has changed (from J-state to K-state, or from J-state to SE0).
Page 639: Portable Device Detection Interrupt
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS)  Puts the port in which the EOFERR interrupt is generated into the idle state. 28.3.3.16 Portable device detection interrupt A portable device detection interrupt is generated when the USBFS detects a level change (high to low or low to high) in the PDDET output from the USB-PHY.
Page 640: Transfer Types
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS)  Bits in DCPCFG and DCPMAXP  SQCLR and SQSET bits in DCPCTR  Bits in PIPECFG, PIPEMAXP, and PIPEPERI ...
Page 641: Response Pid
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) the transfer ended. Two transaction counters are provided:  The PIPEnTRN register that specifies the number of transactions to be executed ...
Page 642: Data Pid Sequence Bit
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS)  STALL setting: PID = STALL is set in the following cases, and issuing of tokens is automatically stopped: ...
Page 643: Null Auto Response Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.3.4.11 Null auto response mode For bulk IN transfer pipes, zero-length packets are continuously transmitted when the PIPEnCTR.ATREPM bit is set to To transition from normal mode to null auto response mode, specify null auto response mode while pipe operation is disabled (response PID = NAK).
Page 644: Fifo Port Functions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.19 Buffer clearing methods Mode for automatically clearing FIFO buffer Clearing FIFO buffer on the the FIFO buffer after reading the Auto buffer clear mode for clearing mode CPU side...
Page 645: Dma Transfers (D0Fifo And D1Fifo Ports)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Table 28.21 FIFO port access by pipe Pipe Access method Port that can be used CPU access CFIFO port register ...
Page 646: Control Transfers In Host Controller Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.3.9.1 Control transfers in host controller mode (1) Setup stage The USQREQ, USBVAL, USBINDX, and USBLENG registers are used to transmit USB requests for setup transactions. Writing the setup packet data to the registers and then writing 1 to the DCPCTR.SUREQ bit transmits the specified data for the setup transaction.
Page 647: Bulk Transfers (Pipes 1 To 5)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) = BUF cannot be set, and the data stage cannot be terminated. Using the VALID bit function, the USBFS can suspend the current request being processed when it receives a new USB request during a control transfer and return a response to the latest request.
Page 648: Interval Counter For Interrupt Transfers In Host Controller Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.3.11.1 Interval counter for interrupt transfers in host controller mode Specify the transaction interval for interrupt transfers in the PIPEPERI.IITV[2:0] bits. (1) The USBFS issues interrupt transfer tokens based on this interval.Counter initialization The USBFS initializes the interval counter under the following conditions: ...
Page 649: Data-Pid
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) In device controller mode:  There is no data to be sent in the FIFO buffer at token receive time in the IN (transmitting) direction ...
Page 650 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) counter enables the functions as shown in Table 28.25. In host controller mode, the USBFS generates the token issuance timing, and the interval counter operation is the same as that for interrupt transfers.
Page 651 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) USB bus PID bit setting Token Token Token Token Token Token Token Token not issued not issued issued not issued issued...
Page 652 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) USB bus PID bit setting Token Token Token Token Token reception reception reception reception is not waited is not waited is waited is waited...
Page 653 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) When the FIFO buffer is ready to transmit data when an IN token is received, the data is transferred and a normal response is returned.
Page 654 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS)  When IITV = 0: The buffer flush operation starts from the first frame after the pipe is enabled. ...
Page 655: Sof Interpolation Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.3.13 SOF Interpolation Function In device controller mode, if packet reception is disabled at intervals of 1 ms because the SOF packet is corrupted or missing, the USBFS interpolates the SOF.
Page 656: Transfer Schedule
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 28.3.14.2 Transfer schedule This section describes the transfer scheduling within a frame of the USBFS. After the USBFS sends an SOF, the transfer is performed in the following sequence: 1.
Page 657 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) current of 7 to 13 µA on the D+ line. The other method is to wait for 300 to 900 ms after VBUS is detected. Note 2.
Page 658: Processing When Host Controller Is Selected
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Detect VBUS Set BATCHGE0 bit Set CNEN bit Data Contact Detection Data Contact Set RPDME0 bit (software waiting method) Detection Set IDPSRCE0 bit (hardware...
Page 659 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) 2. Enable the portable device detection circuit. 3. Monitor the portable device detection signal, and start driving the D- line if the detection signal is high. 4.
Page 660 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) Figure 28.21 show the process flow for steps 1 to 4 and the process flow for steps a to b, respectively. Portable device detection processing Drive VBUS PD detection circuit enabled...
Page 661: Usage Notes
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) D-Line Drive Control Drive VBUS Set VDMSRCE0 bit Connection detected? Clear VDMSRCE0 bit (within 10 ms) Normal state Disconnection detected? Set VDMSRCE0 bit (within 200 ms)
Page 662 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 28. USB 2.0 Full-Speed Module (USBFS) unexpected interrupt might occur at this time, causing the VBINT and OVRCR bits in INTSTS0 and INTSTS1, or other interrupt status flags to set to 1.
Page 663: Serial Communications Interface (Sci)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Serial Communications Interface (SCI) 29.1 Overview The Serial Communications Interface (SCI) is configurable to five asynchronous and synchronous serial interfaces: ...
Page 664 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Table 29.1 SCI specifications (2 of 2) Parameter Description Asynchronous mode Data length 7, 8, or 9 bits Transmission stop bit 1 or 2 bits Parity...
Page 665 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Internal Module data bus peripheral bus SCMR RDRHL FRDRH TDRHL FTDRH MDDR SSR/SSR_SMCI/ FRDRL FTDRL PCLK SSR_FIFO PCLK/4 Baud rate SCR/SCR_SMCI generator...
Page 666: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Table 29.2 SCI I/O pins (2 of 2) Channel Pin name Input/Output Function SCI1 SCK1 Input/Output SCI1 clock input/output RXD1/SCL1/ Input/Output SCI1 receive data input...
Page 667: Receive 9-Bit Data Register (Rdrhl)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 29.2.3 Receive 9-bit Data Register (RDRHL) Address(es): SCI0.RDRHL 4007 0010h, SCI1.RDRHL 4007 0030h, SCI4.RDRHL 4007 0090h, SCI9.RDRHL 4007 0130h Value after reset: RDRHL is a 16-bit register that stores received data.
Page 668: Transmit Data Register (Tdr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Symbol Bit name Description Parity Error Flag 0: No parity error occurred in the first data of FRDRH and FRDRL 1: A parity error occurred in the first data of FRDRH and FRDRL.
Page 669: Transmit 9-Bit Data Register (Tdrhl)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 29.2.6 Transmit 9-Bit Data Register (TDRHL) Address(es): SCI0.TDRHL 4007 000Eh, SCI1.TDRHL 4007 002Eh, SCI4.TDRHL 4007 008Eh, SCI9.TDRHL 4007 012Eh Value after reset: TDRHL is a 16-bit register that stores transmit data.
Page 670: Transmit Shift Register (Tsr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) transfer bit. This register is valid only in asynchronous mode, including multi-processor mode and clock synchronous mode. When the SCI detects that the TSR register is empty, it transmits data written in FTDRH and FTDRL into TSR and starts serial transmission.
Page 671 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Symbol Bit name Description Communication Mode 0: Asynchronous mode or simple IIC mode R/W* 1: Clock synchronous mode or simple SPI mode. Note 1.
Page 672: (Scmr.smif = 1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 29.2.10 Serial Mode Register for Smart Card Interface Mode (SMR_SMCI) (SCMR.SMIF = 1) Address(es): SCI0.SMR_SMCI 4007 0000h, SCI1.SMR_SMCI 4007 0020h, SCI4.SMR_SMCI 4007 0080h,...
Page 673: (Scmr.smif = 0)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Table 29.3 Combinations of SCMR.BCP2 bit and SMR_SMCI.BCP[1:0] bits (2 of 2) SCMR.BCP2 bit SMR_SMCI.BCP[1:0] bits Number of base clock cycles for 1-bit transfer period 372 clock cycles (S = 372)* 256 clock cycles (S = 256)* Note 1.
Page 674 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Symbol Bit name Description TEIE Transmit End Interrupt Enable 0: SCIn_TEI interrupt request is disabled 1: SCIn_TEI interrupt request is enabled. MPIE Multi-Processor Interrupt Enable Valid in asynchronous mode when SMR.MP = 1:...
Page 675: (Scmr.smif = 1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) flags in SSR are not affected and the previous values are saved. When FIFO operation is selected and reception is halted by setting the RE bit to 0, the RDF, ORER, FER, PER, and DR flags in SSR_FIFO are not affected and the previous values are saved.
Page 676 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Symbol Bit name Description Transmit Interrupt Enable 0: SCIn_TXI interrupt request is disabled 1: SCIn_TXI interrupt request is enabled. x: Don’t care Note 1.
Page 677: Serial Status Register (Ssr) For Non-Smart Card Interface And Non-Fifo Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 29.2.13 Serial Status Register (SSR) for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0 and FCR.FM = 0) Address(es): SCI0.SSR 4007 0004h,...
Page 678 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) flag (Parity Error Flag) The PER flag indicates that a parity error occurs during reception in asynchronous mode and the reception ends abnormally.
Page 679: (Scmr.smif = 0 And Fcr.fm = 1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI)  When data is read from the RDR register. Note: Do not clear RDRF flag by accessing RDRF bit in SSR register unless communication is aborted. TDRE flag (Transmit Data Empty...
Page 680 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) flag (Receive Data Ready Flag) The DR flag indicates that the amount of data stored in the Receive FIFO Data Register (FRDRHL) falls below the specified receive triggering number, and that no subsequent data is received after the elapse of 15 ETUs (Elementary Time Units) from the last stop bit in asynchronous mode.
Page 681 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) occurs while data is received. When the SCR.RE bit is set to 0, the FER flag is not affected and the previous state is kept. ORER flag (Overrun Error...
Page 682: (Scmr.smif = 1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 29.2.15 Serial Status Register for Smart Card Interface Mode (SSR_SMCI) (SCMR.SMIF = 1) Address(es): SCI0.SSR_SMCI 4007 0004h, SCI1.SSR_SMCI 4007 0024h, SCI4.SSR_SMCI 4007 0084h,...
Page 683 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) [Setting condition]  When a parity error is detected during reception. Although receive data is transferred to RDR when the parity error occurs, no SCIn_RXI interrupt request occurs.
Page 684: Smart Card Mode Register (Scmr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 29.2.16 Smart Card Mode Register (SCMR) Address(es): SCI0.SCMR 4007 0006h, SCI1.SCMR 4007 0026h, SCI4.SCMR 4007 0086h, SCI9.SCMR 4007 0126h BCP2 —...
Page 685: Bit Rate Register (Brr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI)  Simple IIC mode. SINV (Transmitted/Received Data Invert) The SINV bit inverts the transmit/receive data logic level. This bit does not affect the logic level of the parity bit. To invert the parity bit, invert the PM bit in SMR or SMR_SMCI.
Page 686 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Table 29.5 Relationship between N setting in BRR and bit rate B SEMR settings BGDM ABCS ABCSE Mode BRR setting Error Asynchro-...
Page 687 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Table 29.8 Base clock settings in smart card interface mode (2 of 2) SCMR.BCP2 bit SMR_SMCI.BCP[1:0] bits Base clock cycles for 1-bit period 186 clock cycles 512 clock cycles 32 clock cycles...
Page 688 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Note: In this example, SEMR.ABCS = 0, SEMR.ABCSE = 0, and SEMR.BGDM = 0. When either the ABCS or BGDM bit is set to 1, the bit rate doubles. When both ABCS and BGDM are set to 1, the bit rate quadruples.
Page 689 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Table 29.11 Maximum bit rate for each operating frequency in asynchronous mode (2 of 2) SEMR settings SEMR settings Maximum Maximum PCLK...
Page 690 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Table 29.12 Maximum bit rate with external clock input in asynchronous mode (2 of 2) Maximum bit rate (bps) PCLK (MHz) External input clock (MHz) SEMR.ABCS bit = 0...
Page 691 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Table 29.15 BRR settings for different bit rates in smart card interface mode, n = 0, S = 372 Operating frequency PCLK (MHz) 7.1424 10.00...
Page 692: Modulation Duty Register (Mddr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Operating frequency PCLK (MHz) Bit rate (bps) Error (%) Error (%) Error (%) 100 k* -21.9 -14.1 -3.9 250 k -6.3 350 k...
Page 693 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) The initial value of MDDR is FFh. Bit [7] in this register is fixed to 1. The CPU can read the MDDR register, but this register is only writable when the TE and RE bits in SCR/SCR_SMCI are Table 29.19 Relationship between MDDR setting (M) and bit rate (B) when bit rate modulation function is used SEMR settings...
Page 694: Serial Extended Mode Register (Semr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Operating frequency PCLK (MHz) 12.288 Bit rate BGDM Error BGDM Error BGDM Error (bps) 38400 0.03 (256)* 0.00 0.00 57600 0.03...
Page 695 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Symbol Bit name Description ABCSE Asynchronous Mode Valid only in asynchronous mode with SCR.CKE[1] = 0: Extended Base Clock 0: Clock cycle number for 1-bit period is determined with combination of Select 1 BGDM and ABCS in SEMR...
Page 696: Noise Filter Setting Register (Snfr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) RXDESEL (Asynchronous Start Bit Edge Detection Select) The RXDESEL bit selects the detection method of the start bit for reception in asynchronous mode. When a break occurs, set this bit to 1 to stop reception, or to start reception without retaining the RXDn pin input at high level for the period of one data frame or longer after completion of the break.
Page 697: I 2 C Mode Register 2 (Simr2)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Symbol Bit name Description b2, b1 — Reserved These bits are read as 0. The write value should be 0. b7 to b3 IICDL[4:0] SDA Delay Output Select...
Page 698: I 2 C Mode Register 3 (Simr3)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) because of a wait inserted by another device, for example. The SCLn clock signal is not synchronized if this bit is 0. The SCLn clock signal is generated according to the rate selected in the BRR regardless of the level input on the SCLn pin.
Page 699: I 2 C Status Register (Sisr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) IICRSTAREQ bit to 1. [Setting condition]  Writing 1 to the bit. [Clearing condition]  When generation of a restart condition is complete. IICSTPREQ (Stop Condition Generation When a stop condition is to be generated, set both the IICSDAS[1:0] and IICSCLS[1:0] bits to 01b and set the...
Page 700: Spi Mode Register (Spmr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Symbol Bit name Description — Reserved The read value is undefined — Reserved This bit is read as 0 b5, b4 —...
Page 701: Fifo Control Register (Fcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) (Master Slave Select) The MSS bit selects between master and slave operation in simple SPI mode. The functions of the TXDn and RXDn pins are reversed when the MSS bit is set to 1, so that data is received through the TXDn pin and transmitted through the RXDn pin.
Page 702 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Symbol Bit name Description b11 to b8 RTRG[3:0] Receive FIFO Data Trigger Valid only in asynchronous mode, including multi-processor, or Number clock synchronous mode: 0000: Trigger number 0...
Page 703: Fifo Data Count Register (Fdr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 29.2.27 FIFO Data Count Register (FDR) Address(es): SCI0.FDR 4007 0016h, SCI1.FDR 4007 0036h — — — T[4:0] — —...
Page 704: Compare Match Data Register (Cdr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) ORER (Overrun Error Flag) The ORER bit reflects the value in SSR_FIFO.ORER. FNUM[4:0] bits (Framing Error Count) The value in the FNUM[4:0] bits indicates the amount of data stored in the FRDRHL register with a framing error. PNUM[4:0] bits (Parity Error...
Page 705 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Symbol Bit name Description IDSEL ID Frame Select Valid only in asynchronous mode, including multi-processor: 0: Always compare data regardless of the MPB bit value 1: Compare data when the MPB bit is 1 (ID frame).
Page 706: Serial Port Register (Sptr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) The write value should be 0 for any mode other than asynchronous mode. 29.2.31 Serial Port Register (SPTR) Address(es): SCI0.SPTR 4007 001Ch,...
Page 707: Serial Data Transfer Format
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Idle state (mark state) Serial data Start bit Transmit/receive data Parity bit Stop bit 1 bit 7, 8 or 9 bits 1 or 0 bit 1 or 2 bits One unit of transfer data (character or frame)
Page 708 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Table 29.22 Serial transfer formats (asynchronous mode) (2 of 2) SCMR setting SMR setting Serial transfer format and frame length CHR1 STOP 8-bit data...
Page 709: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 29.3.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the bit rate.
Page 710: Double-Speed Operation And Frequency Of 6 Times The Bit Rate
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) When the SCI uses its internal clock, the clock can be output from the SCKn pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, Figure 29.4 shows.
Page 711: Address Match (Receive Data Match Detection) Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI)  After reception is complete, if it is terminated with SCR.RE = 0 without reading the RDR register, then RTS remains high.
Page 712 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Data (ID1) Data (Data1) Start bit Stop bit Start bit Parity Parity SCIn_AM SCI0_DCUF DCME DCMF flag SCIn_RXI interrupt flag (ICU.IELSRn.IR) RDRF flag DPER flag...
Page 713 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Data (Data0) Data (ID1) Start bit Stop bit Start bit MPB Stop bit Start bit SCIn_AM SCI0_DCUF DCME DCMF flag SCIn_RXI interrupt flag (ICU.IELSRn.IR)
Page 714: Sci Initialization In Asynchronous Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 29.3.7 SCI Initialization in Asynchronous Mode Before transmitting and receiving data, start by writing the initial value 00h to SCR, and then continue through the SCI procedure (select non-FIFO or FIFO) shown in Figure 29.7 Figure...
Page 715: Serial Data Transmission In Asynchronous Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Start initialization [ 1 ] Set FCR.FM, TFRST, and RFRST to 1. This enables FIFO mode and clears the FIFOs. Set the trigger values in FCR.TTRG[3:0], RTRG[3:0], and RSTRG[3:0] bits.
Page 716 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) requests are in use, set TIE to 0 (an SCIn_TXI interrupt request is disabled) and TEIE to 1 (an SCIn_TEI interrupt request is enabled) in the SCR register after the last of the data to be transmitted is written to the TDR from the handling routine for SCIn_TXI requests.
Page 717 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) CTSn_RTSn pin Data Start bit Parity bit Stop bit D7 0/1 1 D7 0/1 Idle state 0 D0 D1 0 D0 (mark state) SCR.TE bit...
Page 718 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] SCI Initialization: Set data transmission. After SCR.TE is set to 1, 1 is output for a frame (preamble), and transmission is enabled.
Page 719 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Data Register Transmit data in FTDRH, FTDRL Length Setting FTDRHL FTDRH FTDRL SCMR. SMR. CHR1 7 bits — 7-bit transmit data —...
Page 720: Serial Data Reception In Asynchronous Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] SCI initialization: Initialization [ 1 ] Set data transmission. After SCR.TE is set to 1, 1 is output for a frame Start data transmission (preamble), and transmission is enabled.
Page 721 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) SCR is 1, an SCIn_ERI interrupt request is generated. 5. If a frame error is detected, the FER flag in the SSR is set to 1 and receive data is transferred to RDR .
Page 722 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 0 before resuming reception. In addition, be sure to read RDR or RDRHL during overrun error processing. When reception is forcibly terminated by setting the RE bit in SCR to 0 during operation, read RDR or RDRHL because the received data that is not read might be left in RDR or RDRHL.
Page 723 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] Initialization SCI initialization: Set data reception. Start data reception [2] [3] Receive error processing and break detection: If a receive error occurs, an SCIn_ERI interrupt is [ 2 ] generated.
Page 724 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) [ 3 ] Error processing SSR.ORER flag = 1? Overrun error processing [ 6 ] [ 6 ] Processing in response to an overrun error: Read the RDR.
Page 725 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) In asynchronous mode, 0 is written to the MPB flag bit in the FRDRH register. Data that corresponds to the data length is written to FRDRH and FRDRL.
Page 726 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] Initialization SCI initialization: Start data reception Set data reception. [2] [3] Receive error processing and break detection: If a receive error occurs, an SCIn_ERI interrupt Read ORER , PER, FER, and DR...
Page 727 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) [ 3 ] Error processing SSR_FIFO.ORER flag = 1? Overrun error processing [ 6 ] [ 6 ] Processing in response to an overrun error: FRDRHL is read and a space is made in FRDRHL.
Page 728: Multi-Processor Communications Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 29.4 Multi-Processor Communications Function The multi-processor communication function enables the SCI to transmit and receive data by sharing a communication line between multiple processors, using asynchronous serial communication in which the multi-processor bit is added.
Page 729: Multi-Processor Serial Data Transmission
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Transmitting station Communication line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04)
Page 730 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Initialization [ 1 ] [ 1 ] SCI initialization: Start data transmission Set data transmission. After SCR.TE is set to 1, 1 is output for a frame, and transmission is enabled.
Page 731 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Data Register Transmit data in FTDRH, FTDRL Length Setting FTDRHL FTDRH FTDRL SCMR. SMR. CHR1 7 bits MPBT —...
Page 732: Multi-Processor Serial Data Reception
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Initialization [ 1 ] [ 1 ] SCI initialization: Start data transmission Set data transmission. After SCR.TE is set to 1, 1 is output for a frame, and transmission is enabled.
Page 733 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Data (ID1) Data (Data1) Start bit Stop bit Start bit Stop bit Idle state (mark state) MPIE SCIn_RXI interrupt flag (IELSRn.IR RDR value MPIE = 0...
Page 734 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] SCI initialization: [ 1 ] Initialization Set data reception. [ 2 ] ID reception cycle: Set SCR.MPIE to 1 and wait for ID reception.
Page 735 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) [ 5 ] Error processing SSR.ORER flag = 1? Overrun error processing [ 6 ] [ 6 ] Processing in response to an overrun error: Read the RDR .
Page 736 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Data Register Receive data in FRDRH, FRDRL Length Setting FRDRHL FRDRH FRDRL SCMR. SMR. CHR1 7 bits — ORER 7-bit receive data 8 bits...
Page 737: Operation In Clock Synchronous Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] SCI initialization: Initialization [ 1 ] Set data reception. [ 2 ] ID reception cycle: Start data reception Set SCR.MPIE to 1 and wait for ID reception.
Page 738: Clock
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Within the SCI, the transmitter and receiver are independent units, enabling full-duplex communications by using a common clock. Both the transmitter and the receiver have a double-buffered structure, so that the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer.
Page 739: Sci Initialization In Clock Synchronous Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) (a) Non-FIFO selected when all of the following conditions are satisfied  The value of the RE or TE bit in SCR is 1 ...
Page 740 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] Set FCR.FM to 0. Start initialization [ 2 ] Set the clock selection in SCR. Set SCR.TIE, RIE, TE, RE, and TEIE to 0 [ 3 ] Set SIMR1.IICM to 0.
Page 741: Serial Data Transmission In Clock Synchronous Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Start initialization [ 1 ] Set FCR.FM, TFRST, and RFRST to 1. This enables FIFO mode and clears the FIFOs. Set the trigger values in FCR.TTRG[3:0], RTRG[3:0], and RSTRG[3:0].
Page 742 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) data to be transmitted is written to TDR. 3. 8-bit data is sent from the TXDn pin in synchronization with the output clock when the clock output mode is specified, and in synchronization with the input clock when the use of an external clock is specified.
Page 743 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) CTSn_RTSn pin Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 SCR.TE bit SCIn_TXI interrupt flag (IELSRn.IR SSR.TEND flag SCIn_TXI interrupt...
Page 744 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] SCI initialization: [ 1 ] Initialization Set data transmission. [ 2 ] Writing transmit data to TDR by an SCIn_TXI interrupt Start transmission request: When transmit data is transferred from TDR to TSR, a...
Page 745: Serial Data Reception In Clock Synchronous Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) signal is suspended until the CTSn_RTSn input signal is low and while the CTSE bit in SPMR is 1. 4.
Page 746 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) In serial data reception, the SCI operates as follows: 1. When the value of SCR.RE becomes 1, the CTSn_RTSn pin goes low. 2.
Page 747 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Synchronization clock Serial data Bit 6 Bit 7 Bit 0 Bit 7 Bit 0 SCIn_RXI interrupt flag (IELSRn.IR* SSR.ORER flag SCIn_RXI SCIn_RXI interrupt...
Page 748 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] SCI initialization: Initialization [ 1 ] Set the input port for pins to be used as RXDn pins.
Page 749 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) In serial data reception, the SCI operates as follows: 1. When the value of SCR.RE becomes 1, the CTSn_RTSn pin goes low. 2.
Page 750 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] SCI initialization: Initialization [ 1 ] Set the input port for pins to be used as RXDn pins.
Page 751: Simultaneous Serial Data Transmission And Reception In Clock Synchronous Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 29.5.6 Simultaneous Serial Data Transmission and Reception in Clock Synchronous Mode (1) Non-FIFO selected Figure 29.43 shows an example flow for simultaneous serial transmission and reception operations in clock synchronous mode.
Page 752 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) [ 1 ] SCI initialization: [ 1 ] Initialization The TXDn pin can act as the output pin for transmitted data and the RXDn pin can act as the input pin for received data at the same time.
Page 753: Operation In Smart Card Interface Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 3. Set the TIE, RIE, TE, and RE bits in the SCR register to 1 simultaneously using a single instruction. [ 1 ] SCI initialization: [ 1 ]...
Page 754: Data Format (Except In Block Transfer Mode)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Setting the TE and RE bits in SCR_SMCI to 1 with an IC card disconnected enables closed-loop transmission or reception allowing self-diagnosis.
Page 755 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) In normal transmission/reception Output from the transmitting station When a parity error occurs Output from the transmitting station Output from the receiving station Start bit...
Page 756: Block Transfer Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) (Z) state D7 D6 D5 D4 D3 D2 D1 D0 Dp Figure 29.48 Inverse convention with SDIR in SCMR = 1, SINV in SCMR = 1, and PM in SMR_SMCI = 1 29.6.3 Block Transfer Mode Block transfer mode differs from non-block transfer mode of the smart card interface mode in the following respects:...
Page 757: Sci Initialization
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 372 clocks 372 clocks 186 clocks 186 clocks 371 0 Base clock Start bit Receive data (RXDn) Synchronization sampling timing Data sampling timing Figure 29.49...
Page 758 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Start initialization Set SCR_SMCI.TIE, RIE, TE, RE, TEIE, [ 1 ] and CKE[1:0] to 0 [ 1 ] Stop the communication and initialize SKE[1:0].
Page 759: Serial Data Transmission (Except In Block Transfer Mode)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) In smart card interface mode, even when the TE and RE bits in SCR_SMCI are 0, the clock is continuously output if the clock output setting is used.
Page 760 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) (n + 1)-th transfer nth transfer frame Retransfer frame frame (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 D6 D7 Dp...
Page 761: Serial Data Reception (Except In Block Transfer Mode)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Start Initialization Start data transmission SSR_SMCI.ERS flag = 0? Error processing SCIn_TXI interrupt Write transmit data to TDR Write all transmit data SSR_SMCI.ERS flag = 0? Error processing...
Page 762 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Figure 29.56 shows an example flow of serial data reception. All the processing steps are automatically performed using an SCIn_RXI interrupt request to activate the DMAC or DTC.
Page 763: Clock Output Control
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Start Initialization Start data reception SSR_SMCI.ORER = 0 and SSR_SMCI.PER = 0? Error processing SCIn_RXI interrupt? Read data from RDR All data received? Set SCR_SMCI.RIE and RE to 0 Figure 29.56...
Page 764: Operation In Simple Iic Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Base clock CKE[0] When GM = 0 When GM = 1 Figure 29.57 Clock output control 29.7 Operation in Simple IIC Mode Simple I C bus format is composed of 8 data bits and an acknowledge bit.
Page 765: Generation Of Start, Restart, And Stop Conditions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) SDAn D7-D1 D7-D1 D7-D1 SCLn R/W# DATA DATA Figure 29.59 C bus timing when SLA is 7 bits Indicates a start condition, when the master device changes the level on the SDAn line from high to low while the SCLn line is high.
Page 766: Clock Synchronization
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI)  When the high level on the SCLn line is detected, the setup time for the stop condition is set as half of a bit period at the bit rate determined by the BRR setting ...
Page 767: Sda Output Delay
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) SCLn output from the other device SCLn line Internal SCLn clock Clock driving transfer internally Counting of the period Counting of the period Counting of the period at high level starts...
Page 768: Sci Initialization In Simple Iic Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 29.7.4 SCI Initialization in Simple IIC Mode Before transferring data, write the initial value of 00h to SCR and initialize the interface as shown in the example in Figure 29.63.
Page 769 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Start condition Slave address (7 bits) Transmitted data Stop condition SCLn SDAn ACK/NACK SCIn_TXI interrupt flag (IELSRn.IR* Acceptance of SCIn_TXI interrupt request STI interrupt flag Generation of SCIn_TXI interrupt request Generation of SCIn_TXI interrupt request...
Page 770 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Initialization [1] Initialization for simple IIC mode: For transmission, set the SCR.RIE bit to 0 to disable RXI and ERI interrupts requests.
Page 771: Master Reception In Simple Iic Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 29.7.6 Master Reception in Simple IIC Mode Figure 29.67 shows an example of master reception operation in simple IIC mode and Figure 29.68 shows an example flow of master reception.
Page 772 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) [1] Initialization for simple IIC mode: Initialization Set the RIE bit in SCR to 0. Start of reception Simultaneously set SIMR3.IICSTAREQ to 1 and [2] Generate a start condition.
Page 773: Operation In Simple Spi Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 29.8 Operation in Simple SPI Mode As an extended function, the SCI supports a simple SPI mode that handles transfer in one or multiple master devices and multiple slave devices.
Page 774: Ss Function In Master Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Table 29.24 Pin states by mode and input level on SSn pin Mode Input on SSn pin State of TXDn pin State of RXDn pin State of SCKn pin Master mode*...
Page 775: Sci Initialization In Simple Spi Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) One unit of transfer data (character or frame) (1) When CKPH = 0 SSn pin (slave) SCKn pin (CKPOL = 0) SCKn pin (CKPOL = 1)
Page 776: 29.10 Interrupt Sources
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) are set to 0 and 160 respectively, in asynchronous mode. In this example, the cycle of the base clock is evenly corrected (256/160) and the bit rate is also corrected (160/256).
Page 777 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) If the TIE bit in SCR register is 1, an SCIn_TXI interrupt request is generated when transmit data is transferred from TDR or TDRHL to the TSR.
Page 778: Interrupts In Smart Card Interface Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Table 29.25 SCI interrupt sources with non-FIFO selected (2 of 2) Name Interrupt source Interrupt flag Interrupt enable DTC activation DMAC activation SCIn_AM...
Page 779: Interrupts In Simple Iic Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) SCIn_ERI interrupt request is issued to the CPU instead. The error flag must be cleared. 29.10.5 Interrupts in Simple IIC Mode Table 29.28 lists the interrupt sources in simple IIC mode.
Page 780: Address Mismatch Event Output (Sci0_Dcuf)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) number is in the receive FIFO buffer, 15 ETUs elapse when FIFO is selected and FCR.DRES is 1. (2) Receive data full event output ...
Page 781: 29.14 Usage Notes
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) When SEMR.ABCS = 0 and SEMR.ABCSE = 0, the cycle is 1/16 the period of 1 transfer bit. When SEMR.ABCS = 1 and SEMR.ABCSE = 0, the cycle is 1/8 the period of 1 transfer bit.
Page 782 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) To transmit data in the same transmission mode after cancellation of the low power state: Set the TE bit to 1. 2.
Page 783 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Data Transmission [ 1 ] Data being transmitted is lost. Data can [ 1 ] All data transmitted? be normally transmitted from the CPU by setting the TE bit in SCR/SCR_SMCI to 1, reading SSR/SSR_FIFO/SSR_SMCI, and...
Page 784 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Transition to Software Standby Software Standby mode mode canceled PmnPFS.PMR bit setting (TXDn pin function setting) SPTR.SPB2IO SCR/SCR_SMCI.TE The level at transition to software standby mode is retained...
Page 785 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Data reception [ 1 ] Received data is invalid. [ 1 ] SCIn_RXI interrupt? Read receive data in RDR SCR/SCR_SMCI.RE = 0 Transition to Software Standby mode [ 2 ] Setting for the module-stop state is included.
Page 786: Break Detection And Processing
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Data reception [ 1 ] Received data is invalid. [ 1 ] SCIn_RXI interrupt? Read receive data in RDR SCR/SCR_SMCI.RE = 0 [ 2 ] Setting for the module-stop state is included.
Page 787: Mark State And Production Of Breaks
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) (2) FIFO selected After a framing error is detected and when the SCI detects that continuous receive data is 0 for one frame, reception stops.
Page 788: Restrictions On Using Dmac Or Dtc
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) Set t  1 PCLK cycle + data output delay time for the slave (tDO) + setup time for the master (tSU) before transmission is started when the external clock is used.
Page 789: Notes On Starting Transfer
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) (2) Reading data from RDR (FRDRHL) When using the DMAC or DTC to read RDR and RDRHL, be sure to set the receive data full interrupt (SCIn_RXI) as the activation source of the relevant SCI channel.
Page 790 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 29. Serial Communications Interface (SCI) 1 PCLK cycle + data output delay time for the slave (tDO) + setup time for the master (tSU) Also, wait at least 5 PCLK cycles from the input of the low level on the SSn pin to the start of the external clock input.
Page 791: I 2 C Bus Interface (Iic)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) C Bus Interface (IIC) 30.1 Overview The MCU has a 2-channel I C Bus Interface (IIC). The IIC module conforms with and provides a subset of the NXP I (Inter-Integrated Circuit) bus interface functions.
Page 792 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Table 30.1 IIC specifications (2 of 2) Parameter Description  Transfer error or event occurrences (arbitration detection, NACK, timeout, start or restart condition, or Event link function (output) stop condition)
Page 793 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Power supply for pull-up SCLin SCLout# SDAin SDAout# (Master) SCLin SCLin SCLout# SCLout# SDAin SDAin SDAout# SDAout# (Slave 1) (Slave 2) Figure 30.2...
Page 794: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) 30.2 Register Descriptions 30.2.1 C Bus Control Register 1 (ICCR1) Address(es): IIC0.ICCR1 4005 3000h, IIC1.ICCR1 4005 3100h IICRST SOWP SCLO SDAO...
Page 795 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) IICRST (IIC Bus Interface Internal Reset) The IICRST bit initiates an internal state reset of the IIC. Setting this bit to 1 initiates an IIC reset or internal reset. Whether an IIC reset or internal reset is initiated is determined by setting this bit in combination with the ICE bit.
Page 796: C Bus Control Register 2 (Iccr2)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) 30.2.2 C Bus Control Register 2 (ICCR2) Address(es): IIC0.ICCR2 4005 3001h, IIC1.ICCR2 4005 3101h BBSY — — Value after reset: Symbol Bit name...
Page 797 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) [Clearing conditions]  When 0 is written to the RS bit  When a restart condition is issued (a start condition is detected) ...
Page 798 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC)  When the AL (arbitration-lost) flag in ICSR2 is set to 1  When the R/W# bit appended to the slave address is set to 1 in master mode ...
Page 799: I 2 C Bus Mode Register 1 (Icmr1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) 30.2.3 C Bus Mode Register 1 (ICMR1) Address(es): IIC0.ICMR1 4005 3002h, IIC1.ICMR1 4005 3102h MTWP CKS[2:0] BCWP BC[2:0] Value after reset: Symbol...
Page 800: I 2 C Bus Mode Register 2 (Icmr2)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) 30.2.4 C Bus Mode Register 2 (ICMR2) Address(es): IIC0.ICMR2 4005 3003h, IIC1.ICMR2 4005 3103h DLCS SDDL[2:0] — TMOH TMOL TMOS Value after reset: Symbol...
Page 801: C Bus Mode Register 3 (Icmr3)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) held high and the timeout function is enabled (ICFER.TMOE bit = 1). SDDL[2:0] bits (SDA Output Delay Counter) The SDDL[2:0] bits can be used to delay the SDA output.
Page 802 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) NF[1:0] bits (Noise Filter Stage Select) The NF[1:0] bits select the number of stages in the digital noise filter. For details on the digital noise filter function, see section 30.6, Digital Noise Filter Circuits.
Page 803: I 2 C Bus Function Enable Register (Icfer)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Note: When the WAIT bit value is to be read, be sure to first read the ICDRR. SMBS (SMBus/I C Bus...
Page 804: C Bus Status Enable Register (Icser)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) NACKE (NACK Reception Transfer Suspension Enable) The NACKE bit specifies whether to continue or discontinue the transfer operation when NACK is received from the slave device in transmit mode.
Page 805: C Bus Interrupt Enable Register (Icier)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) When this bit is set to 1, if the received slave address matches the general call address, the IIC recognizes the received slave address as the general call address independently of the slave addresses set in SARLy and SARUy (y = 0 to 2) and performs data receive operation.
Page 806: C Bus Status Register 1 (Icsr1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) ALIE (Arbitration-Lost Interrupt Request Enable) The ALIE bit enables or disables arbitration-lost interrupt (ALIn) requests when the AL flag in ICSR2 is set to 1. To cancel an ALI interrupt request, set the AL flag or the ALIE bit to 0.
Page 807 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Symbol Bit name Description Host Address Detection Flag 0: Host address not detected R/(W) 1: Host address detected. This bit is set to 1 when the received slave address matches the host address (0001 000b).
Page 808: C Bus Status Register 2 (Icsr2)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC)  When the first frame received immediately after a start condition or restart condition is detected matches a value of (device ID (1111 100b) + 0 [W]), with the DIDE bit in ICSER set to 1 (device ID address detection is enabled).
Page 809 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Symbol Bit name Description TEND Transmit End Flag 0: Data being transmitted R/(W) 1: Data transmission complete. TDRE Transmit Data Empty Flag 0: ICDRT contains transmit data...
Page 810 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Table 30.4 Relationship between arbitration-lost generation sources and arbitration-lost enable functions ICFER ICSR2 MALE NALE SALE Error Arbitration-lost generation source ×...
Page 811: I 2 C Bus Wakeup Unit Register (Icwur)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) in ICCR2 set to 0. [Clearing conditions]  When 0 is written to the RDRF bit after reading RDRF = 1 ...
Page 812: C Bus Wakeup Unit Register 2 (Icwur2)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Symbol Bit name Description WUIE Wakeup Interrupt Request Enable 0: Wakeup Interrupt Request (IIC0_WUI) disabled 1: Wakeup Interrupt Request (IIC0_WUI) enabled. Wakeup Function Enable 0: Wakeup function disabled 1: Wakeup function enabled.
Page 813: Slave Address Register Ly (Sarly) (Y = 0 To 2)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC)  When a stop condition is detected with a wakeup event undetected. WUASYF flag (Wakeup Function Asynchronous Operation Status Flag) This flag can place the IIC in PCLKB asynchronous operation when the wakeup function is enabled (ICWUR.WUE = 1).
Page 814: Slave Address Register Uy (Saruy) (Y = 0 To 2)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) SVA[6:0] bits (7-Bit Address/10-Bit Address Lower Bits) When the 7-bit address format is selected (SARUy.FS = 0), the SVA[6:0] bits function as a 7-bit address. When the 10- bit address format is selected (SARUy.FS = 1), these bits combined with the SVA0 bit to form the lower 8 bits of a 10-bit address.
Page 815: I 2 C Bus Bit Rate High-Level Register (Icbrh)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) automatic SCL low-hold operation (see section 30.9, Automatic Low-Hold Function for SCL). When the IIC is used only in slave mode, the BRL[4:0] bits must be set to a value longer than the data setup time * If the digital noise filter is enabled (the NFE bit in ICFER is 1), set the ICBRL register to a value at least one greater than the number of stages in the noise filter.
Page 816: C Bus Transmit Data Register (Icdrt)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Table 30.6 Example of ICBRH/ICBRL settings for transfer rate when SCLE = 0 BRH[4:0] BRL[4:0] Transfer rate (kbps) CKS[2:0] (ICBRH) (ICBRL)
Page 817: C Bus Shift Register (Icdrs)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) 30.2.19 C Bus Shift Register (ICDRS) — — — — — — — — Value after reset: ICDRS is an 8-bit shift register to transmit and receive data.
Page 818: Initial Settings
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Start condition. The master device drives the SDAn line low from high while the SCLn line is high. SLA: Slave address, by which the master device selects a slave device R/W#:...
Page 819: Master Transmit Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Initial settings Set ICE in ICCR1 to 0 SCLn, SDAn pins not driven Set IICRST in ICCR1 to 1 IIC reset Set ICE in ICCR1 to 1 Internal reset, SCLn and SDAn pins in active state...
Page 820 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) communications, write 1 to the ICCR2.SP bit to issue a stop condition. To transmit data with an address in the 10-bit format, start by writing 1111 0b, the 2 upper bits of the slave address, and W to ICDRT as the first address transmission.
Page 821 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Master transmission [1] Initial settings. Initial settings ICCR2.BBSY = 0? [2] Check I C bus occupation and issue a start condition.
Page 822 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Automatic low-hold (to prevent wrong transmission) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (7-bit address + W) Transmit data (DATA 1) Transmit data (DATA 2) TDRE...
Page 823: Master Receive Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) SCLn SDAn A/NA DATA n-2 DATA n-1 DATA n BBSY Transmit data (DATA n) Transmit data (DATA n-1) TDRE TEND RDRF...
Page 824 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) the R bit to place the IIC in master receive mode. 4. Dummy read ICDRR after confirming that the RDRF flag in ICSR2 is 1. Doing so causes the IIC to start output of the SCL clock and start data reception.
Page 825 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Master reception starts Initial settings (1) Initial settings. ICCR2.BBSY = 0? (2) Check I C bus occupation and issue a start condition. ICCR2.ST = 1 ICSR2.TDRE = 1? Write the ICDRT register...
Page 826 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Master reception Initial settings [1] Initial settings. ICCR2.BBSY = 0? [2] Check I C bus occupation and issue a start condition.
Page 827 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Automatic low hold Master transmit mode Master receive mode (to prevent wrong transmission) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY...
Page 828: Slave Transmit Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Automatic low hold (WAIT) Automatic low hold (WAIT) SCLn NACK SDAn DATA n-2 DATA n-1 DATA n BBSY TDRE Receive data (DATA n-2)
Page 829 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Slave transmission [1] Initial settings. Initial settings ICSR2.NACKF = 0? ICSR2.TDRE = 1? Write data to ICDRT [2], [3] Check ACK and set transmit data.
Page 830 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Slave receive mode Slave transmit mode Automatic low hold (to prevent wrong transmission) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY...
Page 831: Slave Receive Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) 30.3.6 Slave Receive Operation In a slave receive operation, the master device outputs the SCL clock and transmit data, and the IIC returns acknowledgments as a slave device.
Page 832 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Automatic low hold (to prevent failure to receive data) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY TDRE Receive data (7-bit address + W)
Page 833: Scl Synchronization Circuit
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) 30.4 SCL Synchronization Circuit To generate the SCL clock, the IIC starts counting the value for the high-level period specified in ICBRH when it detects a rising edge on the SCLn line and drives the SCLn line low when it completes counting.
Page 834: Sda Output Delay Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) 30.5 SDA Output Delay Function The IIC module provides a function for delaying output on the SDA line. The delay can be applied to all output on the SDA line, including issuing of the start, restart, and stop conditions, data, and the ACK and NACK signals.
Page 835: Address Match Detection
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) level matches the output level of the number of effective flip-flop circuit stages as selected in the NF[1:0] bits in ICMR3, the signal level is seen in the subsequent stage.
Page 836 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) 7-bit address format: Slave reception SCLn SDAn 7-bit slave address Data (DATA 1) Data (DATA 2) BBSY Address match AASy Receive data (7-bit address)
Page 837: Detection Of General Call Address
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) [In the case of SAR0L : 7-bit address, SAR1L : 7-bit address, SAR2 : 10-bit address (1)] 1 to 8 7-bit slave address (SAR0L) R/W#...
Page 838: Device Id Address Detection
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) [General call address reception] Data (DATA 1) Data (DATA 2) BBSY AAS0 Receive data (7-bit address) Receive data (DATA 1) AAS1 AAS2 General call address match (0000 000b + W)
Page 839: Host Address Detection
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) [Device-ID reception] Address BBSY Slave address match AASy Device-ID match (1111 100b + R) Device-ID match (1111 100b + W) Receive data (7-bit address/lower 10 bits) TDRE RDRF...
Page 840: Wakeup Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) [Host address reception] SCLn SDAn Data (DATA 1) Data (DATA 2) BBSY AAS0 Receive data (7-bit address) Receive data (DATA 1) AAS1 AAS2...
Page 841: Normal Wakeup Mode 1
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC)  When the wakeup function is enabled, do not use the timeout function  If the transition from Software Standby mode is triggered by an interrupt other than a wakeup interrupt, for example IRQn, the WUF flag is not set to 1.
Page 842 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) IIC normal operation BBSY = 0 [1] Wait until I C bus is free and stay in standby state. MST = 0 &...
Page 843 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) WUE = 1 WUSEN = 0 [1] Start PCLKB to IIC due to other return factor (IRQ). WUASYF = 1 [2] Set WUSEN to 1.
Page 844: Normal Wakeup Mode 2
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) [Normal Wakeup Mode 1] As with the normal operation, ACK response when there is match with own slave address; SCL held low until return. Before wakeup: Own slave ACK response.
Page 845 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) IIC normal operation BBSY = 0 [1] Wait until I C bus is free and stay in standby state. MST = 0 &...
Page 846: Command Recovery Mode/ Eep Response Mode (Special Wakeup Mode)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) [Normal Wakeup Mode 2] IIC holds SCL low until wakeup after its own slave match. ACK response after wakeup. Before wakeup: Own slave –...
Page 847 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) IIC normal operation [1] Wait until I C bus is free and stay in standby state. BBSY = 0 MST = 0 &...
Page 848 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) WUE = 1 [1] Start PCLKB to IIC due to other return factor (IRQ). WUSEN = 0 [2] Set WUSEN to 1.
Page 849: Precautions For Wfi Instruction Execution
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) [Command return mode/ EEP response mode] Reply ACK / NACK in response to own slave address. Reply ACK in response to own slave again after IICRST release after wakeup. Before wakeup: Own slave ACK/NACK response.
Page 850: Nack Reception Transfer Suspension Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Automatic low-hold [Master transmit mode] (to prevent wrong Automatic low-hold (to prevent wrong transmission) Automatic low-hold (to prevent wrong transmission) transmission) SCLn 7-bit slave address...
Page 851: Function To Prevent Failure To Receive Data
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) [Master transmit mode] Automatic low-hold (to prevent wrong transmission) Bus free time (ICBRL) SCLn 7-bit slave address NACK 7-bit slave address SDAn...
Page 852: 30.10 Arbitration-Lost Detection Functions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) function. When the RDRFS bit is set to 1, the RDRF flag (receive data full) in ICSR2 is set to 1 on the rising edge of the SCL clock cycle, and the SCLn line is automatically held low on the falling edge of the 8 SCL clock cycle.
Page 853 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) After a loss in arbitration of mastership, the IIC immediately enters slave receive mode. If a slave address, including the general call address, matches its own address at this time, the IIC continues in slave operation.
Page 854: Function To Detect Loss Of Arbitration During Nack Transmission (Nale Bit)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Bus free (BBSY = 0) start condition issuance (ST = 1) error Bus busy (BBSY =1) start condition issuance (ST = 1) error SDA mismatch PCLKB PCLKB...
Page 855: Slave Arbitration-Lost Detection (Sale Bit)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) The NACK transmission from master A and the ACK transmission from master B conflict. In general, if a conflict like this occurs, master A cannot detect the ACK transmitted by master B and issues a stop condition.
Page 856: 30.11 Start, Restart, And Stop Condition Issuing Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) 30.11 Start, Restart, and Stop Condition Issuing Function 30.11.1 Issuing a Start Condition The IIC issues a start condition when the ST bit in ICCR2 is set to 1. When the ST bit is set to 1, a start condition request is made.
Page 857 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) [Start condition issuing operation] [Restart condition issuing operation] Hold time Setup time Hold time ICBRH ICBRL ICBRH ICBRL ICBRL ICBRH...
Page 858: Issuing A Stop Condition
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Automatic low-hold (to prevent wrong transmission) SCL0 SDA0 7-bit slave address Data (DATA 1) 7-bit slave address BBSY Transmit data (7-bit address + W) Transmit data (DATA 1)
Page 859: 30.12 Bus Hanging
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Setup time Bus free time ICBRL ICBRH ICBRL ICBRH ICBRL ICBRH ICBRL SCLn Issue stop condition ACK/NACK SDAn IIC ...
Page 860: Extra Scl Clock Cycle Output Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) [Timeout function] Start internal Start internal Start internal Start internal Start internal Start internal counter counter counter counter counter counter...
Page 861: Iic Reset And Internal Reset
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC)  When the bus is free (ICCR2.BBSY = 0) or in master mode (ICCR2.MST = 1 and ICCR2.BBSY = 1) ...
Page 862: Packet Error Code (Pec)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) the GPT using the IIC start condition detection interrupt (STIn) and stop condition detection interrupt (SPIn). The measured timeout period must be within the total clock low-level period [slave device] T : 25 ms (maximum) LOW: SEXT...
Page 863: Smbus Host Notification Protocol (Notify Arp Master Command)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Cyclic Redundancy Check (CRC) Calculator. The PEC data in master transmit mode can be generated by writing all transmit data to the CRC Data Input Register (CRCDIR) in the CRC calculator.
Page 864: Buffer Operation For Iicn_Txi And Iicn_Rxi Interrupts
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) (ICSR2.STOP = 1). Note 2. Because IICn_RXI is an edge-detected interrupt, it does not require clearing. Additionally, the ICSR2.RDRF flag (a condition for IICn_RXI) is automatically set to 0 when data is read from ICDRR.
Page 865: 30.16 Event Link Output
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 30. I C Bus Interface (IIC) Table 30.11 State of registers when issuing each condition (2 of 2) IIC reset Internal reset Start or restart Stop condition Registers Reset...
Page 866: Controller Area Network (Can) Module
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Controller Area Network (CAN) Module 31.1 Overview The CAN module uses a message-based protocol to receive and transmit data between multiple slaves and masters in electromagnetically noisy applications.
Page 867 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Table 31.1 CAN module specifications (2 of 2) Parameter Description Software support unit Three software support units: ...
Page 868: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Used for the time stamp function. The timer value when a message is stored in the mailbox is written as the time stamp value.
Page 869 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Symbol Bit name Description b7, b6 TSPS[1:0] Time Stamp Prescaler b7 b6 0 0: Every 1-bit time Select* 0 1: Every 2-bit time 1 0: Every 4-bit time...
Page 870 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module When the TPM bit is 0, ID priority transmit mode is selected and transmission priority complies with the CAN bus arbitration rule, as defined in the ISO11898-1 CAN specification.
Page 871: Bit Configuration Register (Bcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module CPU request has higher priority. RBOC (Forcible Return from Bus-Off) When the RBOC bit is set to 1 in the bus-off state, the CAN module forcibly exits the bus-off state. This bit is automatically set to 0, and the error state changes from bus-off to error-active.
Page 872 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Symbol Bit name Description b15, b14 — Reserved These bits are read as 0. The write value should be 0. b25 to b16 BRP[9:0] Baud Rate Prescaler select*...
Page 873: Mask Register K (Mkrk) (K = 0 To 7)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module 31.2.3 Mask Register k (MKRk) (k = 0 to 7) Address(es): CAN0.MKR0 4005 0400h CAN0.MKR7 4005 041Ch —...
Page 874 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Symbol Bit name Description b28 to b18 SID[10:0] Standard ID Standard ID of the data and remote frames —...
Page 875: Mask Invalid Register (Mkivlr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module 31.2.5 Mask Invalid Register (MKIVLR) Address(es): CAN0.MKIVLR 4005 0428h MB31 MB30 MB29 MB28 MB27 MB26 MB25 MB24 MB23 MB22 MB21...
Page 876 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Table 31.4 CAN0 mailbox memory mapping (2 of 2) Address for CAN0 Mapped message content 4005 0200h + 16 × j + 13 Data byte 7 4005 0200h + 16 ×...
Page 877 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Symbol Bit Name Description b3 to b0 DLC[3:0] Data Length Code 0 0 0 0: Data length = 0 byte 0 0 0 1: Data length = 1 byte 0 0 1 0: Data length = 2 bytes 0 0 1 1: Data length = 3 bytes...
Page 878 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Address(es): CAN0.MB0_D6 4005 020Ch CAN0.MB31_D6 4005 03FCh DATA6 Value after reset: Address(es): CAN0.MB0_D7 4005 020Dh CAN0.MB31_D7 4005 03FDh DATA7 Value after reset: x: Undefined...
Page 879: Mailbox Interrupt Enable Register (Mier)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Extension) The IDE bit sets the ID format to standard ID or extended ID. The IDE bit is enabled when the IDFM[1:0] bits in the CTLR register are 10b (mixed ID mode): ...
Page 880: Mailbox Interrupt Enable Register For Fifo Mailbox Mode (Mier_Fifo)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module 31.2.8 Mailbox Interrupt Enable Register for FIFO Mailbox Mode (MIER_FIFO) Address(es): CAN0.MIER_FIFO 4005 042Ch — — MB29 MB28 —...
Page 881: Message Control Registers For Transmit (Mctl_Txj) (J = 0 To 31)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module 31.2.9 Message Control Registers for Transmit (MCTL_TXj) (j = 0 to 31)  Transmit mode (when the TRMREQ bit is 1 and the RECREQ bit is 0) Address(es): CAN0.MCTL_TX0 4005 0820h CAN0.MCTL_TX31 4005 083Fh...
Page 882 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module  In one-shot transmission mode (RECREQ = 0, TRMREQ = 1, and ONESHOT = 1), when the CAN module detects CAN bus arbitration-lost or CAN bus error.
Page 883: Message Control Register For Receive (Mctl_Rxj) (J = 0 To 31)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module 31.2.10 Message Control Register for Receive (MCTL_RXj) (j = 0 to 31)  Receive mode (when the TRMREQ bit is 0 and the RECREQ bit is 1) Address(es): CAN0.MCTL_RX0 4005 0820h CAN0.MCTL_RX31 4005 083Fh...
Page 884: Receive Fifo Control Register (Rfcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module ONESHOT (One-Shot Enable) When the ONESHOT bit is set to 1 in receive mode (RECREQ = 1 and TRMREQ = 0), the mailbox receives a message only one time.
Page 885 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Symbol Bit name Description b3 to b1 RFUST[2:0] Receive FIFO Unread Message 0 0 0: No unread message Number Status 0 0 1: 1 unread message 0 1 0: 2 unread messages...
Page 886: Receive Fifo Pointer Control Register (Rfpcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module RFEST flag (Receive FIFO Empty Status Flag) The RFEST flag is set to 1 (no unread message in receive FIFO) when the number of unread messages in the receive FIFO is 0.
Page 887: Transmit Fifo Control Register (Tfcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module 31.2.13 Transmit FIFO Control Register (TFCR) Address(es): CAN0.TFCR 4005 084Ah TFEST TFFST — — TFUST[2:0] Value after reset: Symbol Bit name Description...
Page 888: Transmit Fifo Pointer Control Register (Tfpcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Figure 31.3 shows the transmit FIFO mailbox operation. Transmit FIFO mailbox Frame 1 Frame 2 Frame 3 Frame 4 CAN bus Frame 1 Frame 2 Frame 3 Frame 4...
Page 889: Status Register (Str)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module 31.2.15 Status Register (STR) Address(es): CAN0.STR 4005 0842h — RECST TRMST BOST EPST SLPST HLTST RSTST TABST FMLST NMLST TFST RFST SDST NDST...
Page 890 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module TFST flag (Transmit FIFO Status Flag) The TFST flag is set to 1 when the transmit FIFO is not full. The TFST flag is set to 0 when the transmit FIFO is full or normal mailbox mode is selected.
Page 891: Mailbox Search Mode Register (Msmr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module 31.2.16 Mailbox Search Mode Register (MSMR) Address(es): CAN0.MSMR 4005 0853h — — — — — — MBSM[1:0] Value after reset: Symbol Bit name...
Page 892: Channel Search Support Register (Cssr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module MBNST[4:0]  When the respective NEWDATA, SENTDATA or MSGLOST flag is set to 1 for a mailbox with a smaller number than that in MBNST[4:0].
Page 893: Acceptance Filter Support Register (Afsr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Address CAN0 4005 0851h CSSR 8/3 encoder CAN0 4005 0852h MSSR read) (Search result: Channel number 0 read) read) (Search result: Channel number 3 read) read)
Page 894: Error Interrupt Enable Register (Eier)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Figure 31.5 shows the write and read operation in the AFSR register. Address CAN0 When writing* 4005 0856h 3/8 decoder CAN0 When reading...
Page 895: Error Interrupt Factor Judge Register (Eifr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module EWIE bit is 1, an error interrupt request is generated if the EWIF flag is set to 1. EPIE (Error-Passive Interrupt Enable)
Page 896 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Clear the bits to 0 through a software write. If a bit is set to 1 at the same time that software clears it, the bit becomes 1. When setting a single bit to 0 in software, use the transfer instruction (MOV) to ensure that only the specified bit is set to 0 and the other bits are set to 1.
Page 897: Receive Error Count Register (Recr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module In overrun mode with normal mailbox mode, if an overrun occurs in any of the mailboxes 0 through 31, the ORIF flag is set to 1.
Page 898: Error Code Store Register (Ecsr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module 31.2.24 Error Code Store Register (ECSR) Address(es): CAN0.ECSR 4005 0850h EDPM ADEF BE0F BE1F Value after reset: Symbol Bit name Description...
Page 899: Time Stamp Register (Tsr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module ADEF flag (ACK Delimiter Error Flag) The ADEF flag is set to 1 when a form error is detected with the ACK delimiter during transmission. EDPM (Error Display Mode Select)
Page 900 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module CTX0 CRX0 Recessive level CTX0 CRX0 (internal) (internal) Figure 31.6 Connection when listen-only mode is selected (2) Self-test mode 0 (external loopback) Self-test mode 0 is provided for CAN transceiver tests.
Page 901: Modes Of Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module CTX0 CRX0 Recessive level CTX0 CRX0 (internal) (internal) Figure 31.8 Connection when self-test mode 1 is selected 31.3 Modes of Operation The CAN module operation modes include:...
Page 902: Can Halt Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module CTLR.CANM[1:0] bits until the RSTST flag is set to 1. Set the BCR register before exiting CAN reset mode to enter any other modes.
Page 903: Can Sleep Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Table 31.8 Operation in CAN reset mode and CAN halt mode Operation mode Receiver Transmitter Bus-off CAN reset mode CAN module enters CAN reset CAN module enters CAN reset CAN module enters CAN reset mode...
Page 904: Can Operation Mode (Bus-Off State)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module During CAN operation mode, the CAN module may be in one of the following three sub-modes, depending on the status of the CAN bus: ...
Page 905: Data Transfer Rate Configuration
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module 31.4 Data Transfer Rate Configuration This section describes how to configure the data transfer rate. 31.4.1 Clock Setting The CAN module has a CAN clock generator.
Page 906: Mailbox And Mask Register Structure
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Table 31.9 lists data transfer rate examples. Table 31.9 Data transfer rate examples when fCAN = 32 MHz Data transfer rate Tq count P + 1...
Page 907: Acceptance Filtering And Masking Functions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Address CAN0 4005 0400h + 4  k + 0 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1...
Page 908 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module The receive FIFO mailboxes 28 to 31 use two registers, MKR6 and MKR7, for acceptance filtering. The receive FIFO uses two registers, FIDCR0 and FIDCR1, for ID comparison. The EID[17:0], SID[10:0], RTR, and IDE bits in mailbox 28 to mailbox 31 for the receive FIFO are disabled.
Page 909: Reception And Transmission
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module ID setting of MBj_ID Mask bit values Setting of MKIVLR* (j = 0 to 31)* 0: IDs not compared 1: IDs compared ID value of received Setting of MKRk...
Page 910: Reception
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module When configuring a mailbox as a transmit mailbox or a one-shot transmit mailbox:  Before configuring the mailbox, ensure that the MCTL_TXj register is 00h and that there is no pending abort process.
Page 911: Transmission
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Figure 31.19 shows an operation example of data frame reception in overrun mode. The example shows the overrunning of the second message when the CAN module receives two consecutive CAN messages that match the receiving conditions of MCTL_RXj (j = 0 to 31).
Page 912: Interrupt
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Transmission message in mailbox j Transmission message in mailbox k IFS SOF delimiter delimiter CAN bus Next transmission scan Next transmission scan Next transmission scan MCTL_TXj.TRMREQ...
Page 913: Usage Notes
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 31. Controller Area Network (CAN) Module Eight interrupt sources are available for the CAN0 error interrupts. Check the EIFR register to determine the interrupt sources: ...
Page 914: Serial Peripheral Interface (Spi)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Serial Peripheral Interface (SPI) 32.1 Overview The MCU provides two independent channels of the Serial Peripheral Interface (SPI). The SPI channels are capable of high-speed, full-duplex synchronous serial communications with multiple processors and peripheral devices.
Page 915 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Table 32.1 SPI specifications (2 of 2) Parameter Description  A transfer of up to eight commands (for SPI0) can be executed sequentially in looped execution Control in master transfer ...
Page 916 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Internal Module data bus peripheral bus SPBR SPRX SPTX SPCR SSLP SPPCR Baud rate PCLK generator SPSR SPDR/SPDR_HA SPSCR Parity circuit SPSSR...
Page 917: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Table 32.2 SPI pin configuration Channel Pin name Function SPI0 RSPCKA Clock I/O MOSIA Master transmit data I/O MISOA Slave transmit data I/O SSLA0...
Page 918 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) The SSLn0 to SSLn3 pins are not used in clock synchronous operation. The RSPCKn, MOSIn, and MISOn pins handle communications.
Page 919: Spi Slave Select Polarity Register (Sslp)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) 32.2.2 SPI Slave Select Polarity Register (SSLP) Address(es): SPI0.SSLP 4007 2001h, SPI1.SSLP 4007 2101h — — — — SSL3P SSL2P SSL1P SSL0P Value after reset: Symbol...
Page 920: Spi Status Register (Spsr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) MISOn pin and the shift register if the SPCR.MSTR bit is 1, and between the MOSIn pin and the shift register if the SPCR.MSTR bit is 0.
Page 921 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) IDLNF flag (SPI Idle Flag) The IDLNF flag indicates the transfer status of the SPI. [Setting condition] Master mode ...
Page 922 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) UDRF flag (Underrun Error Flag) The UDRF flag indicates the occurrence of an underrun error. [Setting condition]  When the serial transfer begins with the SPCR.MSTR bit set to 0 (slave mode), SPCR.SPE bit set to 1, and the transmission data not prepared, triggering an underrun error.
Page 923: Spi Data Register (Spdr/Spdr_Ha)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) 32.2.5 SPI Data Register (SPDR/SPDR_HA) Address(es): SPI0.SPDR 4007 2004h, SPI1.SPDR 4007 2104h Value after reset: Value after reset: Address(es): SPI0.SPDR_HA 4007 2004h,...
Page 924 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) SPI data register Transmit buffer SPTX0 Transmit data Shift register Receive data Receive buffer SPRX0 Figure 32.3 Configuration of SPDR/SPDR_HA (SPI1) The transmit and receive buffers each have four stages for SPI0 and one stage for SPI1.
Page 925 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) SPTX0 SPTX1 SPTX2 SPTX3 Write access + Setting of the SPFC[1:0] bits Figure 32.4 Configuration of SPDR/SPDR_HA for write access (SPI0) SPTX0 Figure 32.5 Configuration of SPDR/SPDR_HA for write access (SPI1)
Page 926 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) SPRX0 SPRX1 SPRX2 SPRX3 Read access to receive buffer + Setting of the SPFC[1:0] bits SPTX0 SPTX1 SPTX2 SPTX3 Read access to transmit buffer + SPRDTD...
Page 927: Spi Sequence Control Register (Spscr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) 32.2.6 SPI Sequence Control Register (SPSCR) Address(es): SPI0.SPSCR 4007 2008h — — — — — SPSLN[2:0] Value after reset: Symbol Bit name Description...
Page 928: Spi Bit Rate Register (Spbr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Symbol Bit name Description b6 to b4 SPECM[2:0] SPI Error Command 0 0 0: SPCMD0 0 0 1: SPCMD1 0 1 0: SPCMD2 0 1 1: SPCMD3 1 0 0: SPCMD4...
Page 929: Spi Data Control Register (Spdcr)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Table 32.3 Relationship between SPBR settings, BRDV[1:0] settings, and bit rates (2 of 2) Bit rate SPBR (n) BRDV[1:0] bits (N) Division ratio PCLK = 32 MHz...
Page 930 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) When the transmission data with the number of frames specified by the SPFC[1:0] bits are written to the SPDR/ SPDR_HA register, the SPI clears the SPSR.SPTEF flag to 0 and begins transmitting.
Page 931: Spi Clock Delay Register (Spckd)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) 32.2.10 SPI Clock Delay Register (SPCKD) Address(es): SPI0.SPCKD 4007 200Ch, SPI1.SPCKD 4007 210Ch — — — — — SCKDL[2:0] Value after reset: Symbol...
Page 932: Spi Next-Access Delay Register (Spnd)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) 32.2.12 SPI Next-Access Delay Register (SPND) Address(es): SPI0.SPND 4007 200Eh, SPI1.SPND 4007 210Eh — — — — — SPNDL[2:0] Value after reset: Symbol...
Page 933: Spi Command Registers (Spcmdm) (M =0 To 7 For Spi0; M = 0 For Spi1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) SPPE (Parity Enable) The SPPE bit enables or disables the parity function. When the SPCR.TXMD bit is 0 and this bit is 1, the parity bit is added to transmit data and parity checking is performed for receive data.
Page 934 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Symbol Bit name Description b6 to b4 SSLA[2:0] SSL Signal Assertion Setting 0 0 0: SSL0 0 0 1: SSL1 0 1 0: SSL2 0 1 1: SSL3 1 x x: Setting prohibited...
Page 935 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) CPOL (RSPCK Polarity Setting) The CPOL bit sets the RSPCK polarity of the SPI in master mode or slave mode. Data communications between SPI modules require the same RSPCK polarity setting between the modules.
Page 936: Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) 32.3 Operation In this section, the serial transfer period means a period from the beginning of driving valid data to the fetching of the final valid data.
Page 937: Controlling The Spi Pins
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Table 32.5 Relationship between SPCR settings and SPI modes (2 of 2) Slave (clock Master (clock Slave (SPI Single-master (SPI Multi-master (SPI synchronous...
Page 938: Spi System Configuration Examples
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Note 4. When SSLn0 is at the non-active level or the SPCR.SPE bit is 0, the pin state is Hi-Z. Note 5.
Page 939: Single-Master And Multi-Slave With The Mcu Configured As A Master
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) This MCU (slave) SPI master RSPCKn SPCK RSPCK MOSIn MOSI MOSI MISO MISOn MISO SSLn0 SSL0 SSLn1 SSL1 SSL2 SSLn2 SSL3...
Page 940: Single Master And Multi-Slave With The Mcu Configured As A Slave
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) This MCU (master) SPI slave 0 RSPCKn RSPCK SPCK MOSIn MOSI MOSI MISOn MISO MISO SSLn0 SSL0 SSLn1 SSL1 SSLn2 SSL2...
Page 941: Multi-Master And Multi-Slave With The Mcu Configured As A Master
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) SPI master This MCU (slave X) RSPCKn SPCK RSPCK MOSIn MOSI MOSI MISOn MISO MISO SSLn0 SSLX SSL0 SSLn1 SSLY SSL1...
Page 942: Master And Slave In Clock Synchronous Mode With The Mcu Configured As
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) This MCU (master X) This MCU (master Y) RSPCKn RSPCK RSPCK RSPCKn MOSIn MOSI MOSI MOSIn MISOn MISO MISO MISOn SSLn0...
Page 943: Master And Slave In Clock Synchronous Mode With The Mcu Configured As
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) This MCU (master) SPI slave RSPCKn RSPCK SPCK MOSIn MOSI MOSI MISOn MISO MISO SSLn0 SSL0 SSLn1 SSL1 SSLn2 SSL2 SSLn3...
Page 944: Operation When Parity Is Disabled (Spcr2.Sppe = 0)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) (b) Data format with parity enabled When parity is enabled, transmission or reception of data proceeds with the bit-length selected in the SPI data length setting bits in SPI Command Register m (SPCMDm.SPB[3:0] for SPI0, SPCMD0.SPB[3:0] for SPI1).
Page 945 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) In reception, received data is shifted in bit by bit through bit 0 of the shift register. When the R31 to R00 bits are collected after input of the required number of RSPCK cycles, the value in the shift register is copied to the receive buffer.
Page 946 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Transfer start Transmit buffer Bit 23 Bit 31 Bit 0 Copy Output Bit 23 Bit 31 Bit 0 Shift register Transfer end Shift register...
Page 947 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Transfer start Transmit buffer Bit 31 Bit 0 Copy Output Bit 31 Bit 0 Shift register Transfer end Shift register Bit 31 Bit 0...
Page 948: When Parity Is Enabled (Spcr2.Sppe = 1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Transfer start Transmit buffer Bit 31 Bit 0 Copy Output Bit 31 Bit 0 Shift register Transfer end Input Shift register Bit 31...
Page 949 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Transfer start Transmit buffer Bit 31 Bit 0 Parity calculated Parity added Copy Output Bit 31 Bit 0 Shift register Transfer end Shift register...
Page 950 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Transfer start Transmit buffer Bit 23 Bit 31 Bit 0 Parity added Copy Output Bit 23 Bit 31 Bit 0 Shift register Transfer end...
Page 951 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Transfer start Transmit buffer Bit 31 Bit 0 Parity calculated Parity added Bit 31 Bit 0 Copy Output Bit 31 Bit 0 Shift register...
Page 952: Transfer Format
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Transfer start Transmit buffer Bit 31 Bit 0 Parity calculated Parity added Bit 31 Bit 0 Copy Output Bit 31 Bit 0 Shift register...
Page 953: Cpha = 1
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Start Serial transfer period RSPCK cycle RSPCK RSPCKn (CPOL = 0) (CPOL = 0) RSPCKn RSPCK (CPOL = 1) (CPOL = 1) Sampling timing...
Page 954: Data Transfer Modes
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Start Serial transfer period RSPCK cycle RSPCK RSPCKn (CPOL = 0) (CPOL = 0) RSPCKn RSPCK (CPOL = 1) (CPOL = 1) Sampling timing...
Page 955: Transmit-Only Operations (Spcr.txmd = 1)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) The operation of the flags at timings shown in (1) and (2) in Figure 32.28 is as follows: (1) When a serial transfer ends with the SPDR_HA receive buffer empty, the SPI generates a receive buffer full interrupt request (SPIn_SPRI), the SPI sets the SPSR.SPRF flag to 1, and the received data is copied from the shift register to the receive buffer.
Page 956 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) SPCMD0.CPOL bit is 0 for SPI1. Figure 32.27, the SPI performs an 8-bit serial transfer in which the SPCR.TXMD bit is 0, the SPDCR.SPFC[1:0] bits are 00b, the SPCMDm.CPHA bit is 1, and the SPCMDm.CPOL bit is 0 for SPI0, and in which the SPCR.TXMD bit is 0, the SPCMD0.CPHA bit is 1, and the SPCMD0.CPOL bit is 0 for SPI1.
Page 957: Error Detection
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) SPRF flag to 1. Because the shift register is empty on completion of the serial transfer, if the transmit buffer was full before the serial transfer ended, the SPI sets the SPTEF flag to 1 and copies the data in the transmit buffer to the shift register.
Page 958: Overrun Errors
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Table 32.8 Relationship between non-normal transfer operations and SPI error detection function (2 of 2) Operation Occurrence condition SPI operation Error detection ...
Page 959 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) (3) If the serial transfer ends with the OVRF flag set to 1 (an overrun error occurs), the SPI does not copy the data in the shift register to the receive buffer (the SPRF flag is not set to 1).
Page 960: Parity Errors
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Start Start Serial transfer period Serial transfer period SPDR_HA access RSPCK RSPCK cycle cycle Clock is stopped RSPCKn (CPOL = 0) RSPCKn (CPOL = 1)
Page 961: Mode Fault Errors
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) SPSR access RSPCKn (CPHA = 1, CPOL = 0) PERF OVRF Figure 32.35 Operation example of the OVRF and PERF flags The operation of the flags at the timing shown in (1) to (3) in Figure 32.35 is as follows:...
Page 962: Initializing The Spi
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) On detecting an underrun error, the SPI stops driving the output signals and clears the SPCR.SPE bit to 0 (see section 32.3.9, Initializing the SPI).
Page 963 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) (2) Terminating serial transfer Regardless of the SPCMDm.CPHA bit setting, the SPI terminates a serial transfer after transmitting an RSPCKn edge associated with the final sampling timing.
Page 964 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Sequence length setting Determining reference command Loading transfer format settings SPSCR Command pointer control SPCMD0 SPCMD1 SPCMD2 SPCMD3 SPCMD4 SLNDEN SPNDEN...
Page 965 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) SPTX0/SPRX0 Setting 1-1 SPCMD0 Only 1 frame SPTX0/SPRX0 SPTX1/SPRX1 Setting 1-2 SPCMD0 SPCMD0 1st frame 2nd frame SPTX0/SPRX0 SPTX1/SPRX1 SPTX2/SPRX2 Setting 1-3...
Page 966 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) registers. The SPSCR register determines the sequence configuration for serial transfers that are executed by the SPI in master mode.
Page 967 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) SPTX0/SPRX0 SPCMD0 Only 1 frame Figure 32.41 Relationship between the SPI Command Register and the transmit and receive buffers in sequence operations (SPI1) (4) Burst transfer ...
Page 968 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) next transfer that is detected internally.  SPI1 SPI does not support continuous serial transfer (burst transfer), keeping the SSL signal asserted. However, burst transfer can be implemented by controlling the SSL signal output in general-purpose ports.
Page 969 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Table 32.11 Relationship between SPNDEN bit, SPND, and next-access delay SPCMDm.SPNDEN bit SPND.SPNDL[2:0] bits Next-access delay 000b to 111b 1 RSPCK + 2 PCLK 000b 1 RSPCK + 2 PCLK...
Page 970 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Start of initialization in master mode Set SPI Slave Select Polarity • Set polarity of SSL signal Register (SSLP) Set SPI Pin Control Register •...
Page 971 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) (a) Transmit processing flow When transmitting data and when the SPIn_SPII interrupt is enabled, the CPU is notified of the completion of data transmission after the last data write for transmission.
Page 972 For errors from other sources, the SPCR.SPE bit is not cleared and operations for transmission and reception continue. Renesas recommends clearing the SPCR.SPE bit to stop operations for errors other than mode-fault errors. Not doing so leads to updating of the SPSSR.SPECM[2:0] bits for SPI0.
Page 973: Slave Mode Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Error processing Pre-transfer processing Start error processing End of initial settings Error interrupt (SPIn_SPEI) Clear the SPSR.MODF, OVRF, SPSR.MODF/OVRF/PERF/UDRF [1] Clear error sources PERF, and UDRF flags...
Page 974 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) The final sampling timing changes depending on the bit length of transfer data. In slave mode, the SPI data length depends on the SPCMD0.SPB[3:0] bit setting.
Page 975 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Start of initialization in slave mode Set SPI Slave Select Polarity • Set polarity of SSLn0 input signal Register (SSLP) Set SPI Data Control •...
Page 976 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) (a) Transmit processing flow Pre-transfer processing Processing for transmission Start processing End of initial settings for transmission Clear the SPSR.MODF, OVRF, [1] Clear error sources Transmit buffer empty UDRF, and PERF flags...
Page 977: Clock Synchronous Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Error processing flow In slave operation, even when a mode-fault error is generated, the SPSR.MODF flag can be cleared regardless of the state of the SSLn0 pin.
Page 978 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) SPDR_HA register with the transmit buffer empty, that is, data for the next transfer is not set, and the SPSR.SPTEF flag is 1.
Page 979 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Determining reference Sequence length setting Loading transfer format settings command SPSCR Command pointer control SPCMD0 SPCMD1 SPCMD2 SPCMD3 SPCMD4 SLNDEN SPNDEN...
Page 980 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Figure 32.53 shows the relationship between the command and the transmit and receive buffers in the sequence of operations specified by the settings in Table 32.4.
Page 981 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) (b) SPI1 The transfer format in master mode is determined by the SPCMD0, SPBR, SPCKD, SSLND, and SPND registers. Although the SSLni signals are not output in clock synchronous operation, these settings are valid.
Page 982 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) SPTX0/SPRX0 SPCMD0 Only 1 frame Figure 32.56 Relationship between SPI Command Register and transmit and receive buffers in sequence operations (SPI1) (4) Initialization flow Figure 32.57...
Page 983 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Start of initialization in master mode Set SPI Pin Control Register • Set MOSI signal value when transfer is in idle state (SPPCR) Set SPI Bit Rate Register (SPBR) •...
Page 984: Slave Mode Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) 32.3.11.2 Slave mode operation (1) Starting serial transfer When the SPCR.SPMS bit is 1, the first RSPCKn edge triggers the start of a serial transfer in the SPI, and the SPI drives the MISOn output signal.
Page 985: Loopback Mode
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Start of initialization in slave mode Set SPI Data Control • Set number of frames to be used for SPI0 Register (SPDCR) •...
Page 986: Self-Diagnosis Of Parity Bit Function
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Table 32.12 SPLP2 and SPLP bit settings and received data SPPCR.SPLP2 bit SPPCR.SPLP bit Received data Input data from the MOSIn pin or MISOn pin Inverted transmit data Transmit data Transmit data...
Page 987: Interrupt Sources
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) Start of self-diagnosis of parity circuit Select full-duplex synchronous serial communications (SPCR.TXMD = 0). Enable the parity circuit self-diagnosis function (SPCR2.PTE = 1). Enable the parity function (SPCR2.SPPE = 1).
Page 988: Event Link Operation
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI)  Transmit buffer empty  Transmission-completed  Mode fault  Underrun  Overrun  Parity error  SPI idle. In addition, the DTC or DMAC can be activated by the receive buffer full or transmit buffer empty interrupt to perform data transfer.
Page 989: Receive Buffer Full Event Output
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) 32.4.1 Receive Buffer Full Event Output This event signal is output when received data is transferred from the shift register to the SPDR/SPDR_HA on completion of a serial transfer.
Page 990: Usage Notes
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 32. Serial Peripheral Interface (SPI) transmission or the SPCR.SPE bit is cleared by the mode fault or underrun error. 32.5 Usage Notes 32.5.1 Settings for the Module-Stop State The Module Stop Control Register B (MSTPCRB) can enable or disable SPI operation.
Page 991: Cyclic Redundancy Check (Crc) Calculator
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 33. Cyclic Redundancy Check (CRC) Calculator Cyclic Redundancy Check (CRC) Calculator 33.1 Overview The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first communication.
Page 992: Register Descriptions
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 33. Cyclic Redundancy Check (CRC) Calculator 33.2 Register Descriptions 33.2.1 CRC Control Register 0 (CRCCR0) Address(es): CRC.CRCCR0 4007 4000h DORCL — — — GPS[2:0] Value after reset: Symbol...
Page 993: Crc Data Input Register (Crcdir/Crcdir_By)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 33. Cyclic Redundancy Check (CRC) Calculator Symbol Bit name Description CRCSEN Snoop Enable 0: Disabled 1: Enabled. CRCSWR (Snoop-On-Write/Read Switch) The CRCSWR bit selects the direction of access in the address monitoring function. When this bit is set to 0 (initial value), the CRC snoop operation to read a specific register address is valid.
Page 994: Snoop Address Register (Crcsar)
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 33. Cyclic Redundancy Check (CRC) Calculator 33.2.5 Snoop Address Register (CRCSAR) Address(es): CRC.CRCSAR 4007 400Ch — — CRCSA[13:0] Value after reset: Symbol Bit Name Description b13 to b0 CRCSA[13:0]...
Page 995 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 33. Cyclic Redundancy Check (CRC) Calculator 1. Write 83h to CRC Control Register 0 (CRCCR0) CRCCR0 CRCDOR_HA Clear CRCDOR/CRCDOR_HA/CRCDOR_BY 2. Write F0h to the CRC Data Input Register (CRCDIR_BY) CRCDIR_BY CRCDOR_HA CRC code generation...
Page 996 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 33. Cyclic Redundancy Check (CRC) Calculator 1. 8-bit serial reception (LSB-first) CRC code Data Input 2. Write 83h to the CRC Control Register (CRCCR0) CRCCR0 CRCDOR_HA Clear CRCDOR/CRCDOR_HA/CRCDOR_BY...
Page 997: Crc Snoop
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 33. Cyclic Redundancy Check (CRC) Calculator 1. 8-bit serial reception (MSB-first) Data CRC code Input 2. Write C3h to CRC Control Register 0 (CRCCR0) CRCCR0 CRCDOR_HA Clear CRCDOR/CRCDOR_HA/CRCDOR_BY...
Page 998: Usage Notes
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 33. Cyclic Redundancy Check (CRC) Calculator register address in a bus master module such as the CPU, DMA, and DTC, the CRC calculator stores the data in the CRCDIR_BY register and performs CRC calculations.
Page 999: Overview
Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 34. 14-Bit A/D Converter (ADC14) 14-Bit A/D Converter (ADC14) 34.1 Overview The MCU provides a 14-bit successive approximation A/D converter (ADC14) unit. Up to 8 analog input channels are selectable.
Page 1000 Under development Preliminary document Specifications in this document are tentative and subject to change RA4W1 User’s Manual 34. 14-Bit A/D Converter (ADC14) Table 34.1 ADC14 specifications (2 of 3) Parameter Specifications  8 registers for analog input: Data registers - One register for A/D-converted data duplication in double trigger mode - Two registers for A/D-converted data duplication during extended operation in double trigger mode ...

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