NEC PD703114 User Manual page 158

Bit position Bit name
5, 4 CESUD01,
CESUD00
3, 2 IES1011,
IES1010
1, 0 IES1001,
IES1000
Note See 9.2.4 (2) Timer unit mode register 0 (TUM0).
158
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Specifies the valid edge of the TLCR10 pin
CESUD01 CESUD00
0
0
1
1
The setting values of the CESUD01 and CESUD00 bits and the operation of TM10 are
as follows.
00: TM10 cleared after detection of TCLR10 rising edge
01: TM10 cleared after detection of TCLR10 falling edge
10: TM10 holds cleared status while TCLR10 input is low level
11: TM10 holds cleared status while TCLR10 input is high level
Caution The values set to the CESUD01 and CESUD00 bits are valid only in
UDC mode A
Specifies the valid edge of the pin selected using the CSL0 bit of the CSL10 register
(INTP101/INTP100)
IES1011 IES1010
0
0
1
1
Specifies the valid edge of the INTP100 pin
IES1001 IES1000
0
0
1
1
User's Manual U15195EJ5V0UD
Function
Valid edge
0 Falling edge
1 Rising edge
0 Low level
1 High level
Note
.
Valid edge
0 Falling edge
1 Rising edge
0 Setting prohibited
1 Both rising and falling edges
Valid edge
0 Falling edge
1 Rising edge
0 Setting prohibited
1 Both rising and falling edges
(2/2)