Table of Contents
Advertisement
4.6 Wait Function
4.6.1 Programmable wait function
(1) Data wait control registers 0, 1 (DWC0, DWC1)
To facilitate interfacing with low-speed memory or with I/Os, it is possible to insert up to 7 data wait states in
the bus cycle activated for each CS space.
The number of wait states can be specified by program using data wait control registers 0 and 1 (DWC0 and
DWC1). Just after system reset, all blocks have 3 data wait states inserted.
These registers can be read/written in 16-bit units.
Only the DW02, DW01, and DW00 bits are valid in the V850E/IA2. These registers are not affected by other
bit settings.
Cautions 1. The internal ROM area and internal RAM area are not subject to programmable waits
and ordinarily no wait access is carried out. The on-chip peripheral I/O area is also not
subject to programmable wait states, with wait control performed by each peripheral
function only.
2. Write to the DWC0 and DWC1 registers after reset, and then do not change the set
values.
initialization routine until the initial setting of the DWC0 and DWC1 registers is
complete.
settings are complete.
15
14
13
DWC0
0 DW32 DW31 DW30 0 DW22 DW21 DW20 0 DW12 DW11 DW10 0 DW02 DW01 DW00
CSn signal
CS3
15
14
13
DWC1
0 DW72 DW71 DW70 0 DW62 DW61 DW60 0 DW52 DW51 DW50 0 DW42 DW41 DW40
CSn signal
CS7
Bit position
Bit name
14 to 12,
DWn2 to
10 to 8,
DWn0
6 to 4,
(n = 0 to 7)
2 to 0
94
CHAPTER 4 BUS CONTROL FUNCTION
Also, do not access an external memory area other than the one for this
However, it is possible to access external memory areas whose initial
12
11
10
9
8
7
CS2
12
11
10
9
8
7
CS6
Specifies the number of wait states inserted in the CSn space.
DWn2
DWn1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
User's Manual U15195EJ5V0UD
6
5
4
3
2
1
CS1
CS0
6
5
4
3
2
1
CS5
CS4
Function
DWn0
Number of wait states inserted in CSn space
0
Not inserted
1
1
0
2
1
3
0
4
1
5
0
6
1
7
0
Address
After reset
FFFFF484H
3333H
0
Address
After reset
FFFFF486H
3333H
Advertisement
Table of Contents
