NEC PD703114 User Manual page 589

When a low level is input to the RESET pin, the system is reset and each hardware item of the V850E/IA2 is
initialized to its initial status.
When the RESET pin changes from low level to high level, the reset status is released and the CPU starts program
execution. Initialize the contents of various registers as needed within the program.
13.1 Features
• Noise elimination using analog delay (approx. 60 ns) at reset pin (RESET)
13.2 Pin Functions
During a system reset period, most pin output is high impedance (all pins except CLKOUT
V , V , CV , RV , REGOUT, REGIN, AV
SS SS3 SS DD
Thus, if memory is extended externally, a pull-up (or pull-down) resistor must be attached to each pin of ports DH,
DL, CT, and CM. If there are no resistors, the external memory that is connected may be destroyed when these pins
become high impedance.
Similarly, perform pin processing so that on-chip peripheral I/O function signal outputs and output ports are not
affected.
Note In ROMless mode, CLKOUT signals are also output during a reset period. In single-chip mode, CLKOUT
signals are not output until the PMCCM register is set.
Table 13-1 shows the operation status of each pin during a reset period.
Table 13-1. Operation Status of Each Pin During Reset Period
External access pin A16 to A21, AD0 to AD15, LWR,
UWR, RD, ASTB, WAIT
CLKOUT
Note
Port pin Port 0 to 4
Ports CM, CT, DH, DL
Dedicated function pin TO0n0 to TO0n5
(Pins dedicated to timer 0 output)
ANI00 to ANI05, ANI10 to ANI17
(Pins dedicated to A/D converter input)
Note The names of the control pins that function alternately as port pins are omitted.
Remark n = 0, 1
CHAPTER 13 RESET FUNCTION
, AV
DD0
Pin Name
User's Manual U15195EJ5V0UD
, AV , and AV pins).
DD1 SS0 SS1
In Single-Chip Mode
High impedance
(Input port mode)
High impedance
(Input port mode)
High impedance
(Input port mode)
High impedance
(Input port mode)
High impedance
High impedance
(A/D converter input)
Note
, RESET, X2, V
Pin Status
In ROMless Mode
High impedance
Operation
Refer to the description of
the external access pin.
(control mode)
,
DD
589