NEC PD703114 User Manual page 320

V850e/ia2 32-bit single-chip microcontrollers
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Figure 9-60. Clear Operation After Match of CM101 Register Set Value and TM10 Count Value
(Rising edge set as valid edge)
(Rising edge set as valid edge)
(2) Transfer operation
If TM10 becomes 0000H during down counting when the RLEN bit of the TMC10 register is 1 in UDC mode
A, the set value of the CM100 register is transferred to TM10 at the next count clock. The transfer operation
is not performed during up counting.
(Rising edge set as valid edge)
320
CHAPTER 9 TIMER/COUNTER FUNCTION
(a) Down count → Down count
Count clock
TM10
CM101 register
Down count
(b) Down → Up count
Count clock
TM10
CM101 register
Down count
Figure 9-61. Internal Operation During Transfer Operation
Count clock
TM10
CM100 register
Down count
User's Manual U15195EJ5V0UD
TM10 cleared
00FFH
00FEH
0000H
00FEH
Down count
TM10 not cleared
00FFH
00FEH
00FFH
00FEH
Up count
Transfer operation performed.
CM100
0001H
0000H
set value − 1
set value
FFFFH
Down count
FFFFH
0100H
CM100

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