Cautions - NEC PD703114 User Manual

6.14 Cautions

(1) Memory boundary
The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA
targets (external memory, internal RAM, or on-chip peripheral I/O) during DMA transfer.
(2) Transfer of misaligned data
DMA transfer of 16-bit bus width misaligned data is not supported.
If the source or the destination address is set to an odd address, the LSB of the address is forcibly handled
as "0".
(3) Bus arbitration for CPU
The CPU can access external memory, on-chip peripheral I/O, and internal RAM not undergoing DMA
transfer.
While data transfer between external memories or to and from I/O is being performed, the CPU can access
internal RAM.
While data transfer is being executed between internal RAMs, the CPU can access external memory and on-
chip peripheral I/O.
(4) DMA start factors
Do not start two or more DMA channels with the same factor. If two or more DMA channels are started with
the same factor, the DMA channel with a lower priority may be acknowledged before the DMA channel with a
higher priority. Operation is not guaranteed in this case.
(5) Program execution and DMA transfer with internal RAM
Do not execute DMA transfer to/from the internal RAM and an instruction in the internal RAM simultaneously.
(6) Restrictions related to automatic clearing of TCn bit of DCHCn register
The TCn bit of the DCHCn register is automatically cleared to 0 when it is read. When DMA transfer is
executed to transfer data to or from the internal RAM when two or more DMA transfer channels are
simultaneously used, the TCn bit may not be cleared even if it is read after completion of DMA transfer (n = 0
to 3).
Caution This restriction does not apply if one of the following conditions is satisfied.
• Only one channel of DMA transfer is used.
• DMA is not executed to transfer data to or from the internal RAM.
[Preventive measures]
To read the TCn bit of the DCHCn register of the DMA channel that is used to transfer data to or from the
internal RAM, be sure to read the TCn bit three times in a row. This can accurately clear the TCn bit to 0.
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
User's Manual U15195EJ5V0UD