NEC PD703114 User Manual page 202

(5) Compare registers 004, 005, 014, 015 (CM004, CM005, CM014, CM015)
CM0n4 and CM0n5 are 16-bit registers that always compare their value with TM0n. If the value of these
registers matches the value of TM0n, the registers generate an interrupt signal (INTCM0n4 or INTCM0n5).
CM0n4 and CM0n5 are also provided with a buffer register (BFCMn4 or BFCMn5), the contents of which are
transferred to CM0n4 or CM0n5 at the next transfer timing. Transfer is enabled or disabled by the BFTEN bit
of the TMC0n register.
(6) Compare registers 003, 013 (CM003, CM013)
CM0n3 is a 16-bit register that always compare its value with the value of TM0n. If the values match, CM0n3
outputs an interrupt signal (INTCM0n3). CM0n3 controls the maximum count value of TM0n, and if the
values match, it performs the following operations at the next timer count clock.
• In triangular wave setting mode (PWM modes 0, 1):
• Sawtooth wave setting mode (PWM mode 2):
CM0n3 also has a buffer register (BFCMn3) and transfers the buffer contents to CM0n3 at the next transfer
timing. Transfer enable or disable is controlled by the BFTE3 bit of the TMC0n register.
(7) Buffer registers CM00 to CM02, CM04, CM05, CM10 to CM12, CM14, CM15 (BFCM00 to BFCM02,
BFCM04, BFCM05, BFCM10 to BFCM12, BFCM14, BFCM15)
BFCMn0 to BFCMn2, BFCMn4, and BFCMn5 are 16-bit registers that transfer data to the compare register
(CM0n0 to CM0n2, CM0n4, CM0n5) corresponding to each buffer register when an interrupt signal
(INTCM0n3/INTTM0n) is generated.
These registers can be read/written in 16-bit units.
Caution The set values of the BFCMn0 to BFCMn2, BFCMn4, and BFCMn5 registers are transferred
to the CM0n0 to CM0n2, CM0n4, and CM0n5 registers at the following timing (n = 0, 1).
• When TM0CEn bit of TMC0n register = 0: Transfer at the next operation timing after
writing to the BFCMn0 to BFCMn2, BFCMn4, and BFCMn5 registers
• When TM0CEn bit of TMC0n register = 1: The value of the BFCMn0 to BFCMn2, BFCMn4,
and BFCMn5 registers is transferred to the CM0n0 to CM0n2, CM0n4, and CM0n5
registers upon occurrence of INTTM0n or INTCM0n3. At this time, transfer enable or
disable is controlled by the BFTEN bit of the timer control register (TMC0n).
202
CHAPTER 9 TIMER/COUNTER FUNCTION
User's Manual U15195EJ5V0UD
Switches TM0n operation from count up to count
down
Clears the count value of TM0n