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(4) Timer output mode registers 0, 1 (TOMR0, TOMR1)
The TOMRn register controls timer output from the TO0n0 to TO0n5 pins.
To prevent abnormal output from the TO0n0 to TO0n5 pins due to illegal access, data is written to the
TOMRn register in the following two sequences.
(a) Write access to the TOMR write enable register (SPECn), followed by
(b) Write access to the TOMRn register
Write is not enabled via hardware unless these two sequences are implemented.
TOMRn can be read/written in 8-bit units.
Caution When interrupt requests are generated during write access to the TOMRn register (after
write access to the SPECn register and prior to writing to the TOMRn register), write
processing to the TOMRn register may not be performed normally if access to other
addresses is performed using the internal bus during servicing of these interrupts. Add
one of the following processing items during the TOMRn register write routine.
• Prior to write access to the TOMRn register, disable acknowledgment of all interrupts of
the CPU.
• Following write access to the TOMRn register, check that write was performed normally.
7
6
TOMR0
ALVTO
ALVUB
7
6
TOMR1
ALVTO
ALVUB
Bit position
Bit name
7
ALVTO
6
ALVUB
Remark
n = 0, 1
CHAPTER 9 TIMER/COUNTER FUNCTION
5
4
3
ALVVB
ALVWB
TOSP
5
4
3
ALVVB
ALVWB
TOSP
Specifies the active level of the TO0n0, TO0n2, and TO0n4 pins.
0: Active level is low level
1: Active level is high level
Caution Changing the ALVTO bit during TM0n operation (TM0CEn = 1) is
prohibited.
Specifies the output level of the TO0n1 pin.
0: Inverted level of active level set by ALVTO bit
1: Active level set by ALVTO bit
When ALVUB = 1, the output level of TO0n1 output is the same as TO0n0.
Caution Changing the ALVUB bit during TM0n operation (TM0CEn = 1) is
prohibited.
User's Manual U15195EJ5V0UD
2
1
0
0
TOEDG1
TOEDG0
FFFFF57DH
2
1
0
0
TOEDG1
TOEDG0
FFFFF5BDH
Function
(1/2)
Address
After reset
00H
Address
After reset
00H
213
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