NEC PD703114 User Manual page 412

Bit position Bit name
5 RXE0
4, 3 PS1, PS0
Note When reception is disabled, the receive shift register does not detect a start bit. No shift-in processing
or transfer processing to receive buffer register 0 (RXB0) is performed, and the contents of the RXB0
register are retained.
When reception is enabled, the reception shift operation starts, synchronized with the detection of the
start bit, and when the reception of one frame is completed, the contents of the receive shift register
are transferred to the RXB0 register. A reception completion interrupt (INTSR0) is also generated in
synchronization with the transfer to the RXB0 register.
412
CHAPTER 10 SERIAL INTERFACE FUNCTION
Enables/disables reception.
Note
0: Disables reception
1: Enables reception
Cautions 1. Set the RXE0 bit to 1 after setting the UARTCAE0 bit to 1 at
startup. Set the UARTCAE0 bit to 0 after setting the RXE0 bit to
0 to stop.
2. To initialize the reception unit status, clear (0) the RXE0 bit, and
after letting 2 Clock cycles (base clock) elapse, set (1) the RXE0
bit again. If the RXE0 bit is not set again, initialization may not
be successful. (For details about the base clock, refer to 10.2.6
(1) (a) Base clock (Clock).)
Controls parity bit.
PS1 PS0 Transmit operation
0 0 Don't output parity bit
0 1 Output 0 parity
1 0 Output odd parity
1 1 Output even parity
Cautions 1. To overwrite the PS1 and PS0 bits, first clear (0) the TXE0 and
RXE0 bits.
2. If "0 parity" is selected for reception, no parity judgment is
performed. Therefore, no error interrupt is generated because
the PE bit of the ASIS0 register is not set.
• Even parity
If the transmit data contains an odd number of bits with the value "1", the parity
bit is set (1). If it contains an even number of bits with the value "1", the parity
bit is cleared (0). This controls the number of bits with the value "1" contained
in the transmit data and the parity bit so that it is an even number.
During reception, the number of bits with the value "1" contained in the receive
data and the parity bit is counted, and if the number is odd, a parity error is
generated.
• Odd parity
In contrast to even parity, odd parity controls the number of bits with the value
"1" contained in the transmit data and the parity bit so that it is an odd number.
During reception, the number of bits with the value "1" contained in the receive
data and the parity bit is counted, and if the number is even, a parity error is
generated.
User's Manual U15195EJ5V0UD
Function
Receive operation
Receive with no parity
Receive as 0 parity
Judge as odd parity
Judge as even parity
(2/3)