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NEC 78K0S/KA1+ User Manual

8-bit single-chip microcontrollers.
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User's Manual
78K0S/KA1+
8-Bit Single-Chip Microcontrollers
µ
PD78F9221
µ
PD78F9222
Document No.
U16898EJ3V0UD00 (3rd edition)
Date Published July 2005 NS CP(K)
©
Printed in Japan
2003

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   Summary of Contents for NEC 78K0S/KA1+

  • Page 1

    User’s Manual 78K0S/KA1+ 8-Bit Single-Chip Microcontrollers µ PD78F9221 µ PD78F9222 Document No. U16898EJ3V0UD00 (3rd edition) Date Published July 2005 NS CP(K) 2003 © Printed in Japan...

  • Page 2

    [MEMO] User’s Manual U16898EJ3V0UD...

  • Page 3

    NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.

  • Page 4

    NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

  • Page 5

    Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...

  • Page 6

    INTRODUCTION Target Readers This manual is intended for user engineers who wish to understand the functions of the 78K0S/KA1+ in order to design and develop its application systems and programs. The target devices are the following subseries products. µ • 78K0S/KA1+: PD78F9221(T), 78F9222(T), 78F9221(T2), 78F9222(T2), 78F9221(S), 78F9222(S), 78F9221(R), 78F9222(R), 78F9221(A), 78F9222(A), 78F9221(A2), 78F9222(A2)

  • Page 7

    Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: ××× (overscore over pin or signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ...

  • Page 8

    Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the “Semiconductor Device Mount Manual”...

  • Page 9: Table Of Contents

    CONTENTS CHAPTER 1 OVERVIEW......................... 15 Features ............................15 Application Fields ........................15 Ordering Information ......................... 16 Pin Configuration (Top View) ....................17 78K0S/Kx1+ Product Lineup..................... 18 Block Diagram..........................19 Functional Outline ........................20 CHAPTER 2 PIN FUNCTIONS....................... 21 Pin Function List........................21 Pin Functions ..........................

  • Page 10: Table Of Contents

    3.4.6 Based addressing........................46 3.4.7 Stack addressing .........................47 CHAPTER 4 PORT FUNCTIONS ......................48 Functions of Ports ........................48 Port Configuration ........................49 4.2.1 Port 2............................50 4.2.2 Port 3............................51 4.2.3 Port 4............................53 4.2.4 Port 12............................58 4.2.5 Port 13............................60 Registers Controlling Port Functions ..................60 Operation of Port Function .......................65 4.4.1 Writing to I/O port ........................65 4.4.2...

  • Page 11: Table Of Contents

    Operation of 8-Bit Timer 80.....................126 7.4.1 Operation as interval timer ......................126 Notes on 8-Bit Timer 80......................128 CHAPTER 8 8-BIT TIMER H1 ......................129 Functions of 8-Bit Timer H1 ....................129 Configuration of 8-Bit Timer H1 .....................129 Registers Controlling 8-Bit Timer H1..................132 Operation of 8-Bit Timer H1 ....................135 8.4.1 Operation as interval timer/square-wave output ................

  • Page 12: Table Of Contents

    12.2 Interrupt Sources and Configuration ..................214 12.3 Interrupt Function Control Registers..................217 12.4 Interrupt Servicing Operation ....................222 12.4.1 Maskable interrupt request acknowledgment operation.............222 12.4.2 Multiple interrupt servicing ......................224 12.4.3 Interrupt request pending......................226 CHAPTER 13 STANDBY FUNCTION ....................227 13.1 Standby Function and Configuration..................227 13.1.1 Standby function........................227 13.1.2...

  • Page 13: Table Of Contents

    18.7.1 Flash memory programming mode.................... 271 18.7.2 Communication commands ....................... 271 18.7.3 Security settings ........................272 18.8 Flash Memory Programming by Self Writing ................273 18.8.1 Outline of self programming ...................... 273 18.8.2 Cautions on self programming function ..................276 18.8.3 Registers used for self programming function ................

  • Page 14: Table Of Contents

    Debugging Tools (Software) ....................380 APPENDIX B NOTES ON TARGET SYSTEM DESIGN ..............381 APPENDIX C REGISTER INDEX ......................383 Register Index (Register Name)....................383 Register Index (Symbol) ......................385 APPENDIX D LIST OF CAUTIONS .....................387 APPENDIX E REVISION HISTORY......................353 Major Revisions in This Edition....................353 Revision History up to Previous Editions................356 User’s Manual U16898EJ3V0UD...

  • Page 15: Chapter 1 Overview

    CHAPTER 1 OVERVIEW 1.1 Features µ µ O Minimum instruction execution time selectable from high speed (0.2 s) to low speed (3.2 s) (with CPU clock of 10 MHz) O General-purpose registers: 8 bits × 8 registers O ROM and RAM capacities Item Program Memory (Flash Memory) Memory (Internal High-Speed RAM)

  • Page 16: Ordering Information

    P l e a s e r e f e r t o " Q u a l i t y G r a d e s o n N E C S e m i c o n d u c t o r D e v i c e s " ( D o c u m e n t N o . C 1 1 5 3 1 E ) p u b l i s h e d b y NEC Corporation to know the specification of quality grade (standard grade and special grade) on the devices and its recommended applications.

  • Page 17: Pin Configuration (top View)

    CHAPTER 1 OVERVIEW 1.4 Pin Configuration (Top View) 20-pin plastic SSOP Note P121/X1 P20/ANI0 P122/X2 P21/ANI1 P123 P22/ANI2 P23/ANI3 RESET/P34 P130 P31/TI010/TO00/INTP2 P30/TI000/INTP0 P44/RxD6 P43/TxD6/INTP1 P41/INTP3 P42/TOH1 Note In the 78K0S/KA1+, V functions alternately as the ground potential of the A/D converter. Be sure to connect V to a stabilized GND (= 0 V).

  • Page 18: K0s/kx1+ Product Lineup

    CHAPTER 1 OVERVIEW 1.5 78K0S/Kx1+ Product Lineup The following table shows the product lineup of the 78K0S/Kx1+. Part Number 78K0S/KY1+ 78K0S/KA1+ 78K0S/KB1+ Item Number of pins 16 pins 20 pins 30 pins Internal Flash memory 1 KB, 2 KB, 4 KB 2 KB 4 KB 4 KB, 8 KB...

  • Page 19: Block Diagram

    CHAPTER 1 OVERVIEW 1.6 Block Diagram TO00/TI010/P31 Port 2 P20 to P23 16-bit timer/event counter 00 TI000/P30 P30, P31 Port 3 8-bit timer 80 Port 4 P40 to P45 TOH1/P42 8-bit timer H1 78K0S Flash Port 12 P121 to P123 Low-speed memory internal oscillator...

  • Page 20: Functional Outline

    CHAPTER 1 OVERVIEW 1.7 Functional Outline µ µ Item PD78F9221 PD78F9222 Internal Flash memory 2 KB 4 KB memory High-speed RAM 128 bytes 256 bytes Memory space 64 KB X1 input clock (oscillation frequency) Crystal/ceramic/external clock input: 10 MHz (V = 2.0 to 5.5 V) Internal High speed (oscillation...

  • Page 21: Chapter 2 Pin Functions

    CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List (1) Port functions Pin Name Function After Reset Alternate- Function Pin P20 to P23 Port 2. Input ANI0 to ANI3 4-bit I/O port. Can be set to input or output mode in 1-bit units. An on-chip pull-up resistor can be connected by setting software.

  • Page 22

    CHAPTER 2 PIN FUNCTIONS (2) Non-port functions Pin Name Function After Reset Alternate- Function Pin INTP0 Input External interrupt input for which the valid edge (rising edge, Input P30/TI000 falling edge, or both rising and falling edges) can be specified INTP1 P43/TxD6 INTP2...

  • Page 23: Pin Functions

    CHAPTER 2 PIN FUNCTIONS 2.2 Pin Functions 2.2.1 P20 to P23 (Port 2) P20 to P23 constitute a 4-bit I/O port, port 2. In addition to I/O port pins, these pins also have a function to input analog signals to the A/D converter. These pins can be set to the following operation modes in 1-bit units. (1) Port mode P20 to P23 function as a 4-bit I/O port.

  • Page 24: P40 To P45 (port 4)

    CHAPTER 2 PIN FUNCTIONS 2.2.3 P40 to P45 (Port 4) P40 to P45 constitute a 6-bit I/O port, port 4. In addition to I/O port pins, these pins also have functions to output a timer signal, input external interrupt request signals, and input/output the data of the serial interface. These pins can be set to the following operation modes in 1-bit units.

  • Page 25: Av Ref

    CHAPTER 2 PIN FUNCTIONS 2.2.7 X1 and X2 These pins connect an oscillator to oscillate the X1 input clock. X1 and X2 also function as the P121 and P122, respectively. For the setting method for pin functions, see CHAPTER 17 OPTION BYTE. Supply an external clock to X1.

  • Page 26

    CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits Type 2 Type 11 Pull up P-ch enable Data P-ch IN/OUT Output N-ch disable Schmitt-triggered input with hysteresis characteristics Comparator P-ch N-ch Input enable Type 3-C Type 16-B Feedback cut-off P-ch P-ch Data enable...

  • Page 27: Chapter 3 Cpu Architecture

    CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The 78K0S/KA1+ can access up to 64 KB of memory space. Figures 3-1 and 3-2 show the memory maps. µ Figure 3-1. Memory Map ( PD78F9221) F F F F H Special function registers (SFR) 256 ×...

  • Page 28

    CHAPTER 3 CPU ARCHITECTURE µ Figure 3-2. Memory Map ( PD78F9222) F F F F H Special function registers (SFR) 256 × 8 bits F F 0 0 H F E F F H Internal high-speed RAM 256 × 8 bits F E 0 0 H F D F F H Use prohibited...

  • Page 29: Internal Program Memory Space

    CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The 78K0S/KA1+ provides the following internal ROMs (or flash memory) containing the following capacities. Table 3-1.

  • Page 30: Special Function Register (sfr) Area

    CHAPTER 3 CPU ARCHITECTURE 3.1.3 Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see Table 3-3). 3.1.4 Data memory addressing The 78K0S/KA1+ is provided with a wide range of addressing modes to make memory manipulation as efficient as possible.

  • Page 31

    CHAPTER 3 CPU ARCHITECTURE µ Figure 3-4. Data Memory Addressing ( PD78F9222) F F F F H Special function registers (SFR) SFR addressing 256 × 8 bits F F 2 0 H F E 1 F H F F 0 0 H F E F F H Short direct addressing Internal high-speed RAM...

  • Page 32: Processor Registers

    CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0S/KA1+ provides the following on-chip processor registers. 3.2.1 Control registers The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program counter, a program status word, and a stack pointer. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.

  • Page 33

    CHAPTER 3 CPU ARCHITECTURE (d) Carry flag (CY) This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area.

  • Page 34: General-purpose Registers

    CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H). In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL).

  • Page 35: Special Function Registers (sfrs)

    CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike the general-purpose registers, each special function register has a special function. The special function registers are allocated to the 256-byte area FF00H to FFFFH. The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and bit manipulation instructions.

  • Page 36

    CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers (1/2) Address Special Function Register (SFR) Name Symbol Number of Bits Manipulated After Reset Simultaneously 1 Bit 8 Bits 16 Bits √ √ − FF02H Port register 2 Note 1 FF03H Port register 3 √...

  • Page 37

    CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers (2/2) Address Special Function Register (SFR) Name Symbol Number of Bits Manipulated After Reset Simultaneously 1 Bit 8 Bits 16 Bits √ √ − FF80H A/D converter mode register FF81H Analog input channel specify register √...

  • Page 38: Instruction Address Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.

  • Page 39: Immediate Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) to branch. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces. [Illustration] In case of CALL !addr16 and BR !addr16 instructions CALL or BR...

  • Page 40: Register Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) to branch. This function is carried out when the BR AX instruction is executed. [Illustration] User’s Manual U16898EJ3V0UD...

  • Page 41: Operand Address Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods (addressing) are available to specify the register and memory to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] Identifier Description...

  • Page 42: Short Direct Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word. The fixed space where this addressing is applied is the 160-byte space FE80H to FF1FH (FE80H to FEFFH µ...

  • Page 43: Special Function Register (sfr) Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H to FF1FH are accessed with short direct addressing.

  • Page 44

    CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.

  • Page 45: Register Indirect Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces.

  • Page 46: Based Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored.

  • Page 47: Stack Addressing

    CHAPTER 3 CPU ARCHITECTURE 3.4.7 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon interrupt request generation. Stack addressing can be used to access the internal high-speed RAM area only.

  • Page 48: Chapter 4 Port Functions

    CHAPTER 4 PORT FUNCTIONS Functions of Ports The 78K0S/KA1+ has the ports shown in Figure 4-1, which can be used for various control operations. Table 4-1 shows the functions of each port. In addition to digital I/O port functions, each of these ports has an alternate function. For details, refer to CHAPTER 2 PIN FUNCTIONS.

  • Page 49: Port Configuration

    CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Pin Name Function After Reset Alternate- Function Pin P20 to P23 Port 2. Input ANI0 to ANI3 4-bit I/O port. Can be set to input or output mode in 1-bit units. On-chip pull-up resistor can be connected by setting software. Port 3 Can be set to input or output mode in 1- Input...

  • Page 50: Port 2

    CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 2 Port 2 is a 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). When the P20 to P23 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 2 (PU2).

  • Page 51: Port 3

    CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 3 Pins P30 and P31 constitute a 2-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 3 (PM3). When the P30 to P31 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 3 (PU3).

  • Page 52

    CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P31 PU31 P-ch Alternate function PORT Output latch P31/TI010/TO00/INTP2 (P31) PM31 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal User’s Manual U16898EJ3V0UD...

  • Page 53: Port 4

    CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P34 P34/RESET Reset Option byte Read signal Caution Because the P34 pin functions alternately as the RESET pin, if it is used as an input port pin, the function to input an external reset signal to the RESET pin cannot be used. The function of the port is selected by the option byte.

  • Page 54

    CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P40 and P45 PU40, PU45 P-ch PORT Output latch P40, P45 (P40, P45) PM40, PM45 Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 Read signal WR××: Write signal User’s Manual U16898EJ3V0UD...

  • Page 55

    CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P41 and P44 PU41, PU44 P-ch Alternate function PORT Output latch P41/INTP3, (P41, P44) P44/RxD6 PM41, PM44 Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 Read signal WR××: Write signal User’s Manual U16898EJ3V0UD...

  • Page 56

    CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P42 PU42 P-ch PORT Output latch P42/TOH1 (P42) PM42 Alternate function Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 Read signal WR××: Write signal User’s Manual U16898EJ3V0UD...

  • Page 57

    CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P43 PU43 P-ch Alternate function PORT Output latch P43/TxD6/INTP1 (P43) PM43 Alternate function Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 Read signal WR××: Write signal User’s Manual U16898EJ3V0UD...

  • Page 58: Port 12

    CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 12 Port 12 is a 3-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 12 (PM12). When the P123 pin is used as an input port, an on-chip pull-up resistor can be connected by using pull-up resistor option register 12 (PU12).

  • Page 59

    CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P123 PU12 PU123 P-ch PORT Output latch P123 (P123) PM12 PM123 P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 Read signal WR××: Write signal User’s Manual U16898EJ3V0UD...

  • Page 60: Port 13

    CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 13 This is a 1-bit output-only port. Figure 4-12 shows the block diagram of port 13. Figure 4-12. Block Diagram of P130 PORT Output latch P130 (P130) P13: Port register 13 Read signal WR××: Write signal Remark When a reset is input, P130 outputs a low level.

  • Page 61

    CHAPTER 4 PORT FUNCTIONS Figure 4-13. Format of Port Mode Register Address: FF22H After reset: FFH R/W Symbol PM23 PM22 PM21 PM20 Address: FF23H After reset: FFH R/W Symbol PM31 PM30 Address: FF24H After reset: FFH R/W Symbol PM45 PM44 PM43 PM42 PM41...

  • Page 62

    CHAPTER 4 PORT FUNCTIONS Figure 4-14. Format of Port Register Address: FF02H After reset: 00H (Output latch) R/W Symbol Note Note Address: FF03H After reset: 00H (Output latch) R/W Symbol Address: FF04H After reset: 00H (Output latch) R/W Symbol Address: FF0CH After reset: 00H (Output latch) R/W Symbol P123 P122...

  • Page 63

    CHAPTER 4 PORT FUNCTIONS Figure 4-15. Format of Port Mode Control Register 2 Address: FF84H After reset: 00H R/W Symbol PMC2 PMC23 PMC22 PMC21 PMC20 PMC2n Specification of operation mode (n = 0 to 3) Port mode A/D converter mode Table 4-3.

  • Page 64

    CHAPTER 4 PORT FUNCTIONS (4) Pull-up resistor option registers (PU2, PU3, PU4, PU12) These registers are used to specify whether an on-chip pull-up resistor is connected to P20 to P23, P30, P31, P40 to P45, and P123. By setting PU2, PU3, PU4, or PU12, an on-chip pull-up resistor can be connected to the port pin corresponding to the bit of PU2, PU3, PU4, or PU12.

  • Page 65: Operation Of Port Function

    CHAPTER 4 PORT FUNCTIONS Operation of Port Function The operation of a port differs, as follows, depending on the setting of the I/O mode. Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit units.

  • Page 66: Chapter 5 Clock Generators

    CHAPTER 5 CLOCK GENERATORS Functions of Clock Generators The clock generators include a circuit that generates a clock (system clock) to be supplied to the CPU and peripheral hardware, and a circuit that generates a clock (interval time generation clock) to be supplied to the watchdog timer and 8-bit timer H1 (TMH1).

  • Page 67: Configuration Of Clock Generators

    CHAPTER 5 CLOCK GENERATORS Configuration of Clock Generators The clock generators consist of the following hardware. Table 5-1. Configuration of Clock Generators Item Configuration Control registers Processor clock control register (PCC) Preprocessor clock control register (PPCC) Low-speed internal oscillation mode register (LSRCM) Oscillation stabilization time select register (OSTS) Oscillators Crystal/ceramic oscillator...

  • Page 68

    CHAPTER 5 CLOCK GENERATORS Figure 5-1. Block Diagram of Clock Generators Internal bus Oscillation stabilization Preprocessor clock Processor clock time select register (OSTS) control register (PCC) control register (PPCC) OSTS1 OSTS0 PPCC1 PPCC0 PCC1 System clock oscillation Controller stabilization time counter CPU clock STOP Watchdog timer...

  • Page 69: Registers Controlling Clock Generators

    CHAPTER 5 CLOCK GENERATORS Registers Controlling Clock Generators The clock generators are controlled by the following four registers. • Processor clock control register (PCC) • Preprocessor clock control register (PPCC) • Low-speed internal oscillation mode register (LSRCM) • Oscillation stabilization time select register (OSTS) (1) Processor clock control register (PCC) and preprocessor clock control register (PPCC) These registers are used to specify the division ratio of the system clock.

  • Page 70

    CHAPTER 5 CLOCK GENERATORS The fastest instruction of the 78K0S/KA1+ is executed in two CPU clocks. Therefore, the relationship between the CPU clock (f ) and the minimum instruction execution time is as shown in Table 5-2. Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time Note CPU Clock (f Minimum Instruction Execution Time: 2/f...

  • Page 71

    CHAPTER 5 CLOCK GENERATORS (3) Oscillation stabilization time select register (OSTS) This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP mode is released. The wait time set by OSTS is valid only when the crystal/ceramic oscillation clock is selected as the system clock and after the STOP mode is released.

  • Page 72: System Clock Oscillators

    CHAPTER 5 CLOCK GENERATORS System Clock Oscillators The following three types of system clock oscillators are available. • High-speed internal oscillator: Internally oscillates a clock of 8 MHz (TYP.). • Crystal/ceramic oscillator: Oscillates a clock of 1 to 10 MHz. •...

  • Page 73

    CHAPTER 5 CLOCK GENERATORS Figure 5-7 shows examples of incorrect resonator connection. Figure 5-7. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring of connected circuit (b) Crossed signal lines PORT (d) Current flowing through ground line of oscillator (c) Wiring near high fluctuating current (Potential at points A, B, and C fluctuates.) PORT...

  • Page 74: External Clock Input Circuit

    CHAPTER 5 CLOCK GENERATORS Figure 5-7. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched 5.4.3 External clock input circuit This circuit supplies a clock from an external IC to the X1 pin. If external clock input is selected by the option byte as the system clock source, the X2 pin can be used as an I/O port pin.

  • Page 75: Operation Of Cpu Clock Generator

    CHAPTER 5 CLOCK GENERATORS Operation of CPU Clock Generator A clock (f ) is supplied to the CPU from the system clock (f ) oscillated by one of the following three types of oscillators. • High-speed internal oscillator: Internally oscillates a clock of 8 MHz (TYP.). •...

  • Page 76

    CHAPTER 5 CLOCK GENERATORS (a) The internal reset signal is generated by the power-on clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) The option byte is referenced and the system clock is selected. Then the high-speed internal oscillation clock operates as the system clock.

  • Page 77

    CHAPTER 5 CLOCK GENERATORS Figure 5-10. Timing Chart of Default Start by Crystal/Ceramic Oscillator RESET Internal reset System clock Crystal/ceramic CPU clock oscillator clock PCC = 02H, PPCC = 02H Option byte is read. Clock oscillation System clock is selected. stabilization Note 1 (Operation stops...

  • Page 78

    CHAPTER 5 CLOCK GENERATORS Figure 5-11. Status Transition of Default Start by Crystal/Ceramic Oscillation Power application > 2.1 V ±0.1 V Reset by power-on clear Reset signal Crystal/ceramic oscillation selected by option byte Wait for clock oscillation stabilization Start with PCC = 02H, PPCC = 02H Clock division ratio variable during...

  • Page 79

    CHAPTER 5 CLOCK GENERATORS Figure 5-12. Timing of Default Start by External Clock Input RESET Internal reset System clock External clock input CPU clock PCC = 02H, PPCC = 02H Option byte is read. System clock is selected. Note (Operation stops µ...

  • Page 80: Operation Of Clock Generator Supplying Clock To Peripheral Hardware

    CHAPTER 5 CLOCK GENERATORS Operation of Clock Generator Supplying Clock to Peripheral Hardware The following two types of clocks are supplied to the peripheral hardware. • Clock to peripheral hardware (f • Low-speed internal oscillation clock (f (1) Clock to peripheral hardware The clock to the peripheral hardware is supplied by dividing the system clock (f ).

  • Page 81

    CHAPTER 5 CLOCK GENERATORS Figure 5-14. Status Transition of Low-Speed Internal Oscillation Power application > 2.1 V ±0.1 V Reset by power-on clear Reset signal Select by option byte if low-speed internal oscillator can be stopped or not Can be stopped Cannot be stopped Clock source of Clock source of...

  • Page 82: Chapter 6 16-bit Timer/event Counter 00

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Functions of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. (1) Interval timer 16-bit timer/event counter 00 generates interrupt requests at the preset time interval. • Number of counts: 2 to 65536 (2) External event counter 16-bit timer/event counter 00 can measure the number of pulses with a high-/low-level width of valid level pulse width or more of a signal input externally.

  • Page 83: Configuration Of 16-bit Timer/event Counter 00

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 consists of the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 00 Item Configuration Timer counter 16-bit timer counter 00 (TM00) Register 16-bit timer capture/compare registers 000, 010 (CR000, CR010) Timer input TI000, TI010 Timer output...

  • Page 84

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read.

  • Page 85

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins (1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1) CR000 Capture Trigger TI000 Pin Valid Edge ES010 ES000 Falling edge...

  • Page 86

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit capture/compare register 010 (CR010) CR010 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00 (CRC00).

  • Page 87: Registers To Control 16-bit Timer/event Counter 00

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Registers to Control 16-Bit Timer/Event Counter 00 The following six types of registers are used to control 16-bit timer/event counter 00. • 16-bit timer mode control register 00 (TMC00) • Capture/compare control register 00 (CRC00) •...

  • Page 88

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FF60H After reset: 00H Symbol <0> TMC00 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 TMC001 Operating mode and clear TO00 inversion timing selection Interrupt request generation mode selection Operation stop...

  • Page 89

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Capture/compare control register 00 (CRC00) This register controls the operation of the 16-bit capture/compare registers (CR000, CR010). CRC00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets the value of CRC00 to 00H. Figure 6-6.

  • Page 90

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer output control register 00 (TOC00) This register controls the operation of the 16-bit timer/event counter output controller. It sets timer output F/F set/reset, output inversion enable/disable, 16-bit timer/event counter 00 timer output enable/disable, one-shot pulse output operation enable/disable, and output trigger of one-shot pulse by software.

  • Page 91

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) This register is used to set the 16-bit timer counter 00 (TM00) count clock and the TI000, TI010 pin input valid edges. PRM00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets the value of PRM00 to 00H.

  • Page 92

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Cautions 1. Always set data to PRM00 after stopping the timer operation. 2. If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start mode and the capture trigger at the valid edge of the TI000 pin.

  • Page 93: Operation Of 16-bit Timer/event Counter 00

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Operation of 16-Bit Timer/Event Counter 00 6.4.1 Interval timer operation Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-10 allows operation as an interval timer. Setting The basic operation setting procedure is as follows.

  • Page 94

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-10. Control Register Settings for Interval Timer Operation (a) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CRC00 CR000 used as compare register (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM001 PRM000 PRM00...

  • Page 95: External Event Counter Operation

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-12. Timing of Interval Timer Operation Count clock TM00 count value 0000H 0001H 0000H 0001H 0000H 0001H Timer operation enabled Clear Clear CR000 INTTM000 Interrupt request generated Interrupt request generated Remark Interval time = (N + 1) × t N = 0001H to FFFFH (settable range) When the compare register is changed during timer count operation, if the value after 16-bit timer capture/compare register 000 (CR000) is changed is smaller than that of 16-bit timer counter 00 (TM00), TM00 continues counting,...

  • Page 96

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 The external event counter counts the number of external clock pulses to be input to the TI000 pin with using 16-bit timer counter 00 (TM00). TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input. When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is cleared to 0 and the interrupt request signal (INTTM000) is generated.

  • Page 97

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-15. External Event Counter Configuration Diagram Internal bus 16-bit timer capture/compare register 000 (CR000) Match INTTM000 Clear Note Noise eliminator 16-bit timer counter 00 (TM00) OVF00 Valid edge of TI000 Note OVF00 is 1 only when 16-bit timer capture/compare register 000 is set to FFFFH. Figure 6-16.

  • Page 98: Pulse Width Measurement Operations

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer counter 00 (TM00). There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI000 pin.

  • Page 99

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) Pulse width measurement with free-running counter and one capture register Specify both the rising and falling edges as the valid edges of the TI000 pin, by using bits 4 and 5 (ES000 and ES010) of PRM00.

  • Page 100

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-19. Configuration Diagram for Pulse Width Measurement by Free-Running Counter 16-bit timer/counter 00 (TM00) 16-bit timer capture/compare TI000/INTP0/P30 register 010 (CR010) INTTM010 Internal bus Figure 6-20. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) Count clock 0000H...

  • Page 101

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter. Figure 6-21. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000...

  • Page 102

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-22. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) Count clock 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 D2 + 2 TM00 count value TI000 pin input CR010 capture value INTTM010...

  • Page 103

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-23. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) (a) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CRC00 CR000 used as capture register Captures to CR000 at inverse edge Note to valid edge of TI000...

  • Page 104

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-24. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TM00 count value 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1 TI000 pin input CR010 capture value...

  • Page 105

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-25. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (2/2) (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM001 PRM000 PRM00 Selects count clock (setting “11” is prohibited). Specifies rising edge for pulse width detection.

  • Page 106: Square-wave Output Operation

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figure 6-27 for the set value). <3>...

  • Page 107

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-27. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 00 (TOC00) OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 TOC00 Enables TO00 output. Inverts output on match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting “11”...

  • Page 108: Ppg Output Operations

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.5 PPG output operations Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-29 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic operation setting procedure is as follows. <1>...

  • Page 109

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-29. Control Register Settings for PPG Output Operation (a) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 × CRC00 CR000 used as compare register CR010 used as compare register (b) 16-bit timer output control register 00 (TOC00) OSPT00 OSPE00 TOC004...

  • Page 110

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30. Configuration Diagram of PPG Output 16-bit timer capture/compare register 000 (CR000) Clear 16-bit timer counter 00 circuit (TM00) Noise TI000/INTP0/P30 eliminator TO00/TI010/ INTP2/P31 16-bit timer capture/compare register 010 (CR010) Figure 6-31. PPG Output Operation Timing Count clock M −...

  • Page 111: One-shot Pulse Output Operation

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.6 One-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI000 pin input). Setting The basic operation setting procedure is as follows. <1>...

  • Page 112

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-32. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM001 PRM010 PRM00 Selects count clock. Setting invalid (setting “10” is prohibited.) Setting invalid (setting “10”...

  • Page 113

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-33. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC00 to 04H (TM00 count starts) Count clock − − TM00 count 0000H 0001H N + 1 0000H M + 1 M + 2 CR010 set value CR000 set value OSPT00...

  • Page 114

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-34. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM001 PRM000 PRM00 Selects count clock (setting “11” is prohibited). Specifies the rising edge for pulse width detection.

  • Page 115

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-35. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC00 is set to 08H (TM00 count starts) Count clock − − TM00 count value 0000H 0001H 0000H N + 1 N + 2 M + 1 M + 2 CR010 set value...

  • Page 116: Cautions Related To 16-bit Timer/event Counter 00

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Cautions Related to 16-Bit Timer/Event Counter 00 (1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock.

  • Page 117

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Capture register data retention The values of 16-bit timer capture/compare register 0n0 (CR0n0) after 16-bit timer/event counter 00 has stopped are not guaranteed. Remark n = 0, 1 (5) Setting of 16-bit timer mode control register 00 (TMC00) The timer operation must be stopped before writing to bits other than the OVF00 flag.

  • Page 118

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (12) One-shot pulse output with external trigger <1> Do not input the external trigger again while the one-shot pulse is output. To output the one-shot pulse again, wait until the current one-shot pulse output is completed. <2>...

  • Page 119

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (14) Conflicting operations If the register read period and the input of the capture trigger conflict when CR000/CR010 is used as a capture register, the capture trigger input takes precedence and the read data is undefined. Also, if the count stop of the timer and the input of the capture trigger conflict, the captured data is undefined.

  • Page 120

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (17) Changing compare register during timer operation <1> With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a compare register, when changing CR0n0 around the timing of a match between 16-bit timer counter 00 (TM00) and 16-bit timer capture/compare register 0n0 (CR0n0) during timer counting, the change timing may conflict with the timing of the match, so the operation is not guaranteed in such cases.

  • Page 121

    CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (18) Edge detection <1> In the following cases, note with caution that the valid edge of the TI0n0 pin is detected. (a) Immediately after a system reset, if a high level is input to the TI0n0 pin, the operation of the 16-bit timer counter 00 (TM00) is enabled →...

  • Page 122: Chapter 7 8-bit Timer 80

    CHAPTER 7 8-BIT TIMER 80 Function of 8-Bit Timer 80 8-bit timer 80 has an 8-bit interval timer function and generates an interrupt at intervals specified in advance. Table 7-1. Interval Time of 8-Bit Timer 80 Minimum Interval Time Maximum Interval Time Resolution µ...

  • Page 123: Configuration Of 8-bit Timer 80

    CHAPTER 7 8-BIT TIMER 80 Configuration of 8-Bit Timer 80 8-bit timer 80 consists of the following hardware. Table 7-2. Configuration of 8-Bit Timer 80 Item Configuration Timer counter 8-bit timer counter 80 (TM80) Register 8-bit compare register 80 (CR80) Control register 8-bit timer mode control register 80 (TMC80) Figure 7-1.

  • Page 124

    CHAPTER 7 8-BIT TIMER 80 (1) 8-bit compare register 80 (CR80) This 8-bit register always compares its set value with the count value of 8-bit timer/counter 80 (TM80). It generates an interrupt request signal (INTTM80) if the two values match. CR80 is set by using an 8-bit memory manipulation instruction.

  • Page 125: Register Controlling 8-bit Timer 80

    CHAPTER 7 8-BIT TIMER 80 Register Controlling 8-Bit Timer 80 8-bit timer 80 is controlled by 8-bit timer mode control register 80 (TMC80). (1) 8-bit timer mode control register 80 (TMC80) This register is used to enable or stop the operation of 8-bit timer/counter 80 (TM80), and to set the count clock of TM80.

  • Page 126: Operation Of 8-bit Timer 80

    CHAPTER 7 8-BIT TIMER 80 Operation of 8-Bit Timer 80 7.4.1 Operation as interval timer When 8-bit timer 80 operates as an interval timer, it can repeatedly generate an interrupt at intervals specified by the count value set in advance to 8-bit compare register 80 (CR80). To use 8-bit timer 80 as an interval timer, make the following setting.

  • Page 127

    CHAPTER 7 8-BIT TIMER 80 Figure 7-5. Timing of Interval Timer Operation Count clock TM80 count value Clear Clear CR80 TCE80 Count start INTTM80 Interrupt request generated Interrupt request generated Interval time Interval time Remark Interval time = (N + 1) × t N = 00H to FFH User’s Manual U16898EJ3V0UD...

  • Page 128: Notes On 8-bit Timer 80

    CHAPTER 7 8-BIT TIMER 80 Notes on 8-Bit Timer 80 (1) Error when timer starts The time from starting the timer to generation of the match signal includes an error of up to 1.5 clocks. This is because, if the timer is started while the count clock is high, the rising edge may be immediately detected and the counter may be incremented (refer to Figure 7-6).

  • Page 129: Chapter 8 8-bit Timer H1

    CHAPTER 8 8-BIT TIMER H1 Functions of 8-Bit Timer H1 8-bit timer H1 has the following functions. • Interval timer • PWM output mode • Square-wave output Configuration of 8-Bit Timer H1 8-bit timer H1 consists of the following hardware. Table 8-1.

  • Page 130

    Figure 8-1. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode register 1 (TMHMD1) 8-bit timer H 8-bit timer H TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 compare register compare register 11 (CMP11) 01 (CMP01) Decoder TOH1/P42 Selector Output latch...

  • Page 131

    CHAPTER 8 8-BIT TIMER H1 (1) 8-bit timer H compare register 01 (CMP01) This register can be read or written by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 8-2. Format of 8-Bit Timer H Compare Register 01 (CMP01) Address: FF0EH After reset: 00H Symbol...

  • Page 132: Registers Controlling 8-bit Timer H1

    CHAPTER 8 8-BIT TIMER H1 Registers Controlling 8-Bit Timer H1 The following three registers are used to control 8-Bit Timer H1. • 8-bit timer H mode register 1 (TMHMD1) • Port mode register 4 (PM4) • Port register 4 (P4) (1) 8-bit timer H mode register 1 (TMHMD1) This register controls the mode of timer H.

  • Page 133

    CHAPTER 8 8-BIT TIMER H1 Figure 8-4. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF70H After reset: 00H <7> <1> <0> Symbol TMHMD1 TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHE1 Timer operation enable Stop timer count operation (counter is cleared to 0) Enable timer count operation (count operation started by inputting clock) CKS12 CKS11...

  • Page 134

    CHAPTER 8 8-BIT TIMER H1 (2) Port mode register 4 (PM4) This register sets port 4 input/output in 1-bit units. When using the P42/TOH1 pin for timer output, clear PM42 and the output latch of P42 to 0. PM4 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH.

  • Page 135: Operation Of 8-bit Timer H1

    CHAPTER 8 8-BIT TIMER H1 Operation of 8-Bit Timer H1 8.4.1 Operation as interval timer/square-wave output When 8-bit timer counter H1 and compare register 01 (CMP01) match, an interrupt request signal (INTTMH1) is generated and 8-bit timer counter H1 is cleared to 00H. Compare register 11 (CMP11) is not used in interval timer mode.

  • Page 136

    CHAPTER 8 8-BIT TIMER H1 (2) Timing chart The timing of the interval timer/square-wave output operation is shown below. Figure 8-7. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation (01H ≤ CMP01 ≤ FEH) Count clock Count start 01H 00H 8-bit timer counter H1 Clear...

  • Page 137

    CHAPTER 8 8-BIT TIMER H1 Figure 8-7. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP01 = FFH Count clock Count start 8-bit timer counter H1 Clear Clear CMP01 TMHE1 INTTMH1 TOH1 Interval time (c) Operation when CMP01 = 00H Count clock Count start 8-bit timer counter H1...

  • Page 138: Operation As Pwm Output Mode

    CHAPTER 8 8-BIT TIMER H1 8.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register during timer operation is prohibited.

  • Page 139

    CHAPTER 8 8-BIT TIMER H1 <4> When 8-bit timer counter H1 and the CMP11 register match, TOH1 output becomes inactive and the compare register to be compared with 8-bit timer counter H1 is changed from the CMP11 register to the CMP01 register.

  • Page 140

    CHAPTER 8 8-BIT TIMER H1 (2) Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP11 register setting value (M) and CMP01 register setting value (N) are within the following range. 00H ≤ CMP11 (M) < CMP01 (N) ≤ FFH Figure 8-9.

  • Page 141

    CHAPTER 8 8-BIT TIMER H1 Figure 8-9. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP01 = FFH, CMP11 = 00H Count clock 8-bit timer counter H1 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP01 CMP11 TMHE1...

  • Page 142

    CHAPTER 8 8-BIT TIMER H1 Figure 8-9. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP01 = 01H, CMP11 = 00H Count clock 01H 00H 01H 00H 00H 01H 00H 01H 8-bit timer counter H1 CMP01 CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 = 0)

  • Page 143

    CHAPTER 8 8-BIT TIMER H1 Figure 8-9. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP11 (CMP11 = 02H → 03H, CMP01 = A5H) Count clock 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H 8-bit timer counter H1 CMP01...

  • Page 144: Chapter 9 Watchdog Timer

    CHAPTER 9 WATCHDOG TIMER Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of RESF, see CHAPTER 14 RESET FUNCTION.

  • Page 145

    CHAPTER 9 WATCHDOG TIMER Table 9-2. Option Byte Setting and Watchdog Timer Operation Mode Option Byte Setting Low-Speed Internal Oscillator Cannot Be Stopped Low-Speed Internal Oscillator Can Be Stopped by Software Note 1 Watchdog timer clock Fixed to f • Selectable by software (f or stopped) •...

  • Page 146: Configuration Of Watchdog Timer

    CHAPTER 9 WATCHDOG TIMER Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 9-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer mode register (WDTM) Watchdog timer enable register (WDTE) Figure 9-1. Block Diagram of Watchdog Timer Clock Output 16-bit...

  • Page 147: Registers Controlling Watchdog Timer

    CHAPTER 9 WATCHDOG TIMER Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. • Watchdog timer mode register (WDTM) • Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and operation clock of the watchdog timer. This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be written only once after reset is released.

  • Page 148

    CHAPTER 9 WATCHDOG TIMER Cautions 1. Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values. 2. After reset is released, WDTM can be written only once by an 8-bit memory manipulation instruction. If writing is attempted a second time, an internal reset signal is generated.

  • Page 149: Operation Of Watchdog Timer

    CHAPTER 9 WATCHDOG TIMER Operation of Watchdog Timer 9.4.1 Watchdog timer operation when “low-speed internal oscillator cannot be stopped” is selected by option byte The operation clock of watchdog timer is fixed to low-speed internal oscillation clock. After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).

  • Page 150

    CHAPTER 9 WATCHDOG TIMER Figure 9-4. Status Transition Diagram When “Low-Speed Internal Oscillator Cannot Be Stopped” Is Selected by Option Byte Reset WDT clock: f Overflow time: 546.13 ms (MAX.) WDTE = “ACH” Clear WDT counter. WDT clock is fixed to f Select overflow time (settable only once).

  • Page 151: Watchdog Timer Operation When "low-speed Internal Oscillator Can Be Stopped By Software" Is Selected By Option Byte

    CHAPTER 9 WATCHDOG TIMER 9.4.2 Watchdog timer operation when “low-speed internal oscillator can be stopped by software” is selected by option byte The operation clock of the watchdog timer can be selected as either the low-speed internal oscillation clock or the system clock.

  • Page 152

    CHAPTER 9 WATCHDOG TIMER Figure 9-5. Status Transition Diagram When “Low-Speed Internal Oscillator Can Be Stopped by Software” Is Selected by Option Byte Reset WDT clock: f Overflow time: 546.13 ms (MAX.) WDCS4 = 1 WDT clock = f Select overflow time (settable only once).

  • Page 153: Watchdog Timer Operation In Stop Mode (when "low-speed Internal Oscillator Can Be Stopped By Software" Is Selected By Option Byte)

    CHAPTER 9 WATCHDOG TIMER 9.4.3 Watchdog timer operation in STOP mode (when “low-speed internal oscillator can be stopped by software” is selected by option byte) The watchdog timer stops counting during STOP instruction execution regardless of whether the system clock or low-speed internal oscillation clock is being used.

  • Page 154

    CHAPTER 9 WATCHDOG TIMER (2) When the watchdog timer operation clock is the low-speed internal oscillation clock (f ) when the STOP instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is µ...

  • Page 155: Watchdog Timer Operation In Halt Mode (when "low-speed Internal Oscillator Can Be Stopped By Software" Is Selected By Option Byte)

    CHAPTER 9 WATCHDOG TIMER 9.4.4 Watchdog timer operation in HALT mode (when “low-speed internal oscillator can be stopped by software” is selected by option byte) The watchdog timer stops counting during HALT instruction execution regardless of whether the operation clock of the watchdog timer is the system clock (f ) or low-speed internal oscillation clock (f ).

  • Page 156: Chapter 10 A/d Converter

    CHAPTER 10 A/D CONVERTER 10.1 Functions of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to four channels (ANI0 to ANI3) with a resolution of 10 bits. The A/D converter has the following function. •...

  • Page 157

    CHAPTER 10 A/D CONVERTER Table 10-1. Sampling Time and A/D Conversion Time Reference Sampling Conversion = 8 MHz = 10 MHz Note 2 Note 3 Voltage Time Time Sampling Conversion Sampling Conversion Note 1 Range Note 2 Note 3 Note 2 Note 3 Time Time...

  • Page 158: Configuration Of A/d Converter

    CHAPTER 10 A/D CONVERTER Figure 10-2 shows the block diagram of A/D converter. Figure 10-2. Block Diagram of A/D Converter ANI0/P20 Sample & hold circuit ANI1/P21 Voltage comparator D/A converter ANI2/P22 ANI3/P23 Successive approximation register (SAR) Controller INTAD A/D conversion result register (ADCR, ADCRH) ADS1 ADS0...

  • Page 159

    CHAPTER 10 A/D CONVERTER (5) Successive approximation register (SAR) This register compares the sampled analog voltage and the voltage of the D/A converter, and converts the result, starting from the most significant bit (MSB). When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR).

  • Page 160: Registers Used By A/d Converter

    CHAPTER 10 A/D CONVERTER 10.3 Registers Used by A/D Converter The A/D converter uses the following six registers. • A/D converter mode register (ADM) • Analog input channel specification register (ADS) • 10-bit A/D conversion result register (ADCR) • 8-bit A/D conversion result register (ADCRH) •...

  • Page 161

    CHAPTER 10 A/D CONVERTER (1) A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. ADM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 10-3.

  • Page 162

    CHAPTER 10 A/D CONVERTER Notes 2. Be sure to set the FR2, FR1, and FR0, in accordance with the reference voltage so that Notes 2 and 3 below are satisfied. ≥ 2.7 V, f Example When AV = 8 MHz µ...

  • Page 163

    CHAPTER 10 A/D CONVERTER Cautions 2. If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped (ADCS = 0) and then A/D conversion is started, execute two NOP instructions or an instruction equivalent to two machine cycles, and set ADCS to 1. 3.

  • Page 164

    CHAPTER 10 A/D CONVERTER (4) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. It stores the higher 8 bits of a 10-bit resolution result. ADCRH can be read by an 8-bit memory manipulation instruction. Reset signal generation makes ADCRH undefined.

  • Page 165: A/d Converter Operations

    CHAPTER 10 A/D CONVERTER 10.4 A/D Converter Operations 10.4.1 Basic operations of A/D converter <1> Set ADCE to 1. <2> Select one channel for A/D conversion using the analog input channel specification register (ADS), and select the conversion time using FR2 to FR0. <3>...

  • Page 166

    CHAPTER 10 A/D CONVERTER Figure 10-10. Basic Operation of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result ADCR, Conversion ADCRH result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.

  • Page 167: Input Voltage And Conversion Results

    CHAPTER 10 A/D CONVERTER 10.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression.

  • Page 168: A/d Converter Operation Mode

    CHAPTER 10 A/D CONVERTER 10.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI3 by the analog input channel specification register (ADS) and A/D conversion is executed. (1) A/D conversion operation By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register...

  • Page 169

    CHAPTER 10 A/D CONVERTER The setting method is described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Select the channel and conversion time using bits 1 and 0 (ADS1, ADS0) of the analog input channel specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.

  • Page 170: How To Read A/d Converter Characteristics Table

    CHAPTER 10 A/D CONVERTER 10.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).

  • Page 171

    CHAPTER 10 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale − 3/2LSB) when the digital output changes from 1..110 to 1..111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.

  • Page 172: Cautions For A/d Converter

    CHAPTER 10 A/D CONVERTER 10.6 Cautions for A/D Converter (1) Operating current in STOP mode The A/D converter stops operating in the STOP mode. At this time, the operating current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0. (2) Input range of ANI0 to ANI3 Observe the rated range of the ANI0 to ANI3 input voltage.

  • Page 173

    CHAPTER 10 A/D CONVERTER (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AV pin and ANI0 to ANI3 pins. <1> Connect a capacitor with a low equivalent resistance and a high frequency response to the power supply. <2>...

  • Page 174

    CHAPTER 10 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite.

  • Page 175

    CHAPTER 10 A/D CONVERTER (10) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 10-21. Internal Equivalent Circuit of ANIn Pin ANIn LSI internal Table 10-3. Resistance and Capacitance Values (Reference Values) of Equivalent Circuit 4.5 V ≤...

  • Page 176: Chapter 11 Serial Interface Uart6

    CHAPTER 11 SERIAL INTERFACE UART6 11.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.

  • Page 177

    CHAPTER 11 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master.

  • Page 178

    CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-2. LIN Reception Operation Wakeup Synchronous Synchronous Identifier Data field Data field Checksum signal frame break field field field field LIN bus 13 bits Data Data Data reception reception reception reception reception SBF reception <5>...

  • Page 179

    CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-3. Port Configuration for LIN Reception Operation Selector P44/R RXD6 input Port mode (PM44) Output latch (P44) Selector Selector P30/INTP0/TI000 INTP0 input Port mode Port input (PM30) selection control (ISC0) Output latch <ISC0> (P30) 0: Selects INTP0 (P30).

  • Page 180: Configuration Of Serial Interface Uart6

    CHAPTER 11 SERIAL INTERFACE UART6 11.2 Configuration of Serial Interface UART6 Serial interface UART6 consists of the following hardware. Table 11-1. Configuration of Serial Interface UART6 Item Configuration Registers Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers Asynchronous serial interface operation mode register 6 (ASIM6)

  • Page 181

    Figure 11-4. Block Diagram of Serial Interface UART6 Note TI000, INTP0 Filter INTSR6 Reception control INTSRE6 Receive shift register 6 (RXS6) Asynchronous serial Asynchronous serial Asynchronous serial interface Baud rate Receive buffer register 6 interface operation mode interface reception error control register 6 (ASICL6) generator (RXB6)

  • Page 182

    CHAPTER 11 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (RXS6).

  • Page 183: Registers Controlling Serial Interface Uart6

    CHAPTER 11 SERIAL INTERFACE UART6 11.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. • Asynchronous serial interface operation mode register 6 (ASIM6) • Asynchronous serial interface reception error status register 6 (ASIS6) •...

  • Page 184

    CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) RXE6 Enabling/disabling reception Disable reception (synchronously reset the reception circuit). Enable reception PS61 PS60 Transmission operation Reception operation Parity bit not output. Reception without parity Note Output 0 parity.

  • Page 185

    CHAPTER 11 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0.

  • Page 186

    CHAPTER 11 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.

  • Page 187

    CHAPTER 11 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).

  • Page 188

    CHAPTER 11 SERIAL INTERFACE UART6 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).

  • Page 189

    CHAPTER 11 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).

  • Page 190

    CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 SBL61 SBL60 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length.

  • Page 191

    CHAPTER 11 SERIAL INTERFACE UART6 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. By setting 1 to ISC0 and ISC1, the input source to INTP0 and TI000 switches to the input signal from the P44/RxD6 pin.

  • Page 192: Operation Of Serial Interface Uart6

    CHAPTER 11 SERIAL INTERFACE UART6 11.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 11.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode.

  • Page 193: Asynchronous Serial Interface (uart) Mode

    CHAPTER 11 SERIAL INTERFACE UART6 11.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.

  • Page 194

    CHAPTER 11 SERIAL INTERFACE UART6 The relationship between the register settings and pins is shown below. Table 11-2. Relationship Between Register Settings and Pins POWER6 TXE6 RXE6 PM43 PM44 UART6 Pin Function Operation TxD6/INTP1/P43 RxD6/P44 Note Note Note Note × ×...

  • Page 195

    CHAPTER 11 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 11-13 and 11-14 show the format and waveform example of the normal transmit/receive data. Figure 11-13. Format of Normal UART Transmit/Receive Data 1.

  • Page 196

    CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-14. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity...

  • Page 197

    CHAPTER 11 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.

  • Page 198

    CHAPTER 11 SERIAL INTERFACE UART6 (c) Normal transmission When bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1, and then bit 6 (TXE6) of ASIM6 is set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6).

  • Page 199

    CHAPTER 11 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized.

  • Page 200

    CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-16 shows an example of the continuous transmission processing flow. Figure 11-16. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Read ASIF6 TXBF6 = 0? Write TXB6. Transmission completion interrupt occurred?

  • Page 201

    CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-17 shows the timing of starting continuous transmission, and Figure 11-18 shows the timing of ending continuous transmission. Figure 11-17. Timing of Starting Continuous Transmission Start Data (1) Parity Stop Start Data (2) Parity Stop Start INTST6...

  • Page 202

    CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-18. Timing of Ending Continuous Transmission Data (n − 1) Start Start Parity Data (n) Parity Stop Stop Stop INTST6 Data (n − 1) TXB6 Data (n) Data (n − 1) TXS6 Data (n) TXBF6 TXSF6 POWER6 or TXE6...

  • Page 203

    CHAPTER 11 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the R D6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the R D6 pin input is detected.

  • Page 204

    CHAPTER 11 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.

  • Page 205

    CHAPTER 11 SERIAL INTERFACE UART6 (g) Noise filter of receive data The R D6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data.

  • Page 206

    CHAPTER 11 SERIAL INTERFACE UART6 SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 11-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.

  • Page 207: Dedicated Baud Rate Generator

    CHAPTER 11 SERIAL INTERFACE UART6 11.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...

  • Page 208

    CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-24. Configuration of Baud Rate Generator POWER6 Baud rate generator POWER6, TXE6 (or RXE6) Selector 8-bit counter XCLK6 Match detector Baud rate CKSR6: TPS63 to TPS60 BRGC6: MDL67 to MDL60 Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6 RXE6:...

  • Page 209

    CHAPTER 11 SERIAL INTERFACE UART6 (2) Generation of serial clock A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control register 6 (BRGC6). Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6. Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter.

  • Page 210

    CHAPTER 11 SERIAL INTERFACE UART6 (3) Example of setting baud rate Table 11-4. Set Data of Baud Rate Generator Baud Rate = 10.0 MHz = 8.38 MHz = 4.19 MHz [bps] TPS63 to Calculated ERR[%] TPS63 to Calculated ERR[%] TPS63 to Calculated ERR[%] TPS60...

  • Page 211

    CHAPTER 11 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.

  • Page 212

    CHAPTER 11 SERIAL INTERFACE UART6 k − 2 21k + 2 Minimum permissible data frame length: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. − 1 BRmax = (FLmin/11) Brate 21k + 2...

  • Page 213

    CHAPTER 11 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected.

  • Page 214: Chapter 12 Interrupt Functions

    CHAPTER 12 INTERRUPT FUNCTIONS 12.1 Interrupt Function Types There are two types of interrupts: maskable interrupts and resets. • Maskable interrupts These interrupts undergo mask control. When an interrupt request occurs, the standby release signal occurs, and if an interrupt can be acknowledged then the program corresponding to the address written in the vector table address is executed (vector interrupt servicing).

  • Page 215

    CHAPTER 12 INTERRUPT FUNCTIONS Table 12-1. Interrupt Sources Note 1 Interrupt Type Priority Interrupt Source Internal/ Vector Table Basic External Address Configuration Name Trigger Note 2 Type Note 3 Maskable INTLVI Low-voltage detection Internal 0006H INTP0 Pin input edge detection External 0008H INTP1...

  • Page 216

    CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-1. Basic Configuration of Interrupt Function (A) Internal maskable interrupt Internal bus Vector table address generator Interrupt request Standby release signal (B) External maskable interrupt Internal bus External interrupt mode register (INTM0, INTM1) Vector table address generator Edge Interrupt...

  • Page 217: Interrupt Function Control Registers

    CHAPTER 12 INTERRUPT FUNCTIONS 12.3 Interrupt Function Control Registers The interrupt functions are controlled by the following four types of registers. • Interrupt request flag registers (IF0, IF1) • Interrupt mask flag registers (MK0, MK1) • External interrupt mode registers (INTM0, INTM1) •...

  • Page 218

    CHAPTER 12 INTERRUPT FUNCTIONS Interrupt request flag registers (IF0, IF1) An interrupt request flag is set to 1 when the corresponding interrupt request is issued, or when the instruction is executed. It is cleared to 0 by executing an instruction when the interrupt request is acknowledged or when a reset signal is input.

  • Page 219

    CHAPTER 12 INTERRUPT FUNCTIONS Interrupt mask flag registers (MK0, MK1) The interrupt mask flag is used to enable and disable the corresponding maskable interrupts. MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets MK0 and MK1 to FFH. Figure 12-3.

  • Page 220

    CHAPTER 12 INTERRUPT FUNCTIONS External interrupt mode register 0 (INTM0) This register is used to set the valid edge of INTP0 to INTP2. INTM0 is set with an 8-bit memory manipulation instruction. Reset signal generation clears INTM0 to 00H. Figure 12-4. Format of External Interrupt Mode Register 0 (INTM0) Address: FFECH After reset: 00H Symbol...

  • Page 221

    CHAPTER 12 INTERRUPT FUNCTIONS External interrupt mode register 1 (INTM1) INTM1 is used to specify the valid edge for INTP3. INTM1 is set with an 8-bit memory manipulation instruction. Reset signal generation clears INTM1 to 00H. Figure 12-5. Format of External Interrupt Mode Register 1 (INTM1) Address: FFEDH After reset: 00H Symbol...

  • Page 222: Interrupt Servicing Operation

    CHAPTER 12 INTERRUPT FUNCTIONS 12.4 Interrupt Servicing Operation 12.4.1 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. If the interrupt enabled status is in effect (when the IE flag is set to 1), then the request is acknowledged as a vector interrupt.

  • Page 223

    CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-7. Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (Interrupt request generated) ××MK = 0? Interrupt request pending IE = 1? Interrupt request pending Vectored interrupt servicing ××IF: Interrupt request flag ××MK: Interrupt mask flag Flag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable) Figure 12-8.

  • Page 224: Multiple Interrupt Servicing

    CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-9. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last Clock During Instruction Execution) 8 clocks Clock Interrupt Saving PSW and PC, jump servicing MOV A, r to interrupt servicing program Interrupt If an interrupt request flag (××IF) is set at the last clock of the instruction, the interrupt acknowledgment processing starts after the next instruction is executed.

  • Page 225

    CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-10. Example of Multiple Interrupts (1/2) Example 1. Multiple interrupts are acknowledged INTxx servicing INTyy servicing Main processing IE = 0 IE = 0 INTxx INTyy RETI RETI During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupts are generated. Before each interrupt request acknowledgement, the EI instruction is issued, the interrupt mask is released, and the interrupt request acknowledgement enable state is set.

  • Page 226: Interrupt Request Pending

    CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-10. Example of Multiple Interrupts (2/2) Example 3. A priority is controlled by the Multiple interrupts The vector interrupt enable state is set for INTP0, INTP1, and INTTMH1. (Interruption priority INTP0 > INTP1 > INTTMH1 (refer to Table12-1)) INTTNH1 servicing Main processing INTP1 servicing...

  • Page 227: Chapter 13 Standby Function

    CHAPTER 13 STANDBY FUNCTION 13.1 Standby Function and Configuration 13.1.1 Standby function Table 13-1. Relationship Between Operation Clocks in Each Operation Status Status Low-Speed Internal Oscillator System Clock Clock Supplied to Peripheral Note 1 Note 2 Hardware Operation Mode LSRSTOP = 0 LSRSTOP = 1 Reset Stopped...

  • Page 228

    CHAPTER 13 STANDBY FUNCTION (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the system clock oscillator stops, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, select the HALT mode if processing must be immediately started by an interrupt request when the Note operation stop time...

  • Page 229: Registers Used During Standby

    CHAPTER 13 STANDBY FUNCTION 13.1.2 Registers used during standby The oscillation stabilization time after the standby mode is released is controlled by the oscillation stabilization time select register (OSTS). Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATORS. (1) Oscillation stabilization time select register (OSTS) This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP mode is released.

  • Page 230: Standby Function Operation

    CHAPTER 13 STANDBY FUNCTION 13.2 Standby Function Operation 13.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operating statuses in the HALT mode are shown below. Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag clear, the standby mode is immediately cleared if set.

  • Page 231

    CHAPTER 13 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed.

  • Page 232

    CHAPTER 13 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 13-3.

  • Page 233: Stop Mode

    CHAPTER 13 STANDBY FUNCTION 13.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction. Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set.

  • Page 234

    CHAPTER 13 STANDBY FUNCTION (2) STOP mode release Figure 13-4. Operation Timing When STOP Mode Is Released <1> If high-speed internal oscillation clock or external input clock is selected as system clock to be supplied STOP mode is released. STOP mode System clock oscillation CPU clock...

  • Page 235

    CHAPTER 13 STANDBY FUNCTION (a) Release by unmasked interrupt request When an unmasked interrupt request (8-bit timer H1, low-voltage detector, external interrupt request) is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed.

  • Page 236

    CHAPTER 13 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. Figure 13-6. STOP Mode Release by Reset Signal Generation (1) If CPU clock is high-speed internal oscillation clock or external input clock STOP instruction...

  • Page 237: Chapter 14 Reset Function

    CHAPTER 14 RESET FUNCTION The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer overflows (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences.

  • Page 238

    CHAPTER 14 RESET FUNCTION Figure 14-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF LVIRF Clear Reset signal of WDT Clear Reset signal to LVIM/LVIS register RESET Reset signal of POC Internal reset signal Reset signal of LVI Caution The LVI circuit is not reset by the internal reset signal of the LVI circuit.

  • Page 239

    CHAPTER 14 RESET FUNCTION Figure 14-2. Timing of Reset by RESET Input <1> With high-speed internal oscillation clock or external clock input High-speed internal oscillation clock or external clock input Normal operation Reset period CPU clock Normal operation (reset processing, CPU clock) in progress (oscillation stops) RESET...

  • Page 240

    CHAPTER 14 RESET FUNCTION Figure 14-3. Timing of Reset by Overflow of Watchdog Timer <1> With high-speed internal oscillation clock or external clock input High-speed internal oscillation clock or external clock input Reset period Normal operation Normal operation (reset processing, CPU clock) CPU clock (oscillation stops) in progress...

  • Page 241

    CHAPTER 14 RESET FUNCTION Figure 14-4. Reset Timing by RESET Input in STOP Mode <1> With high-speed internal oscillation clock or external clock input STOP instruction is executed. High-speed internal oscillation clock or external clock input Normal Reset period Stop status Normal operation (reset processing, CPU clock) operation CPU clock...

  • Page 242

    CHAPTER 14 RESET FUNCTION Remarks 1. For the reset timing of the power-on-clear circuit and low-voltage detector, refer to CHAPTER 15 POWER-ON-CLEAR CIRCUIT and CHAPTER 16 LOW-VOLTAGE DETECTOR. 2. f : System clock oscillation frequency When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.

  • Page 243

    CHAPTER 14 RESET FUNCTION Table 14-1. Hardware Statuses After Reset Acknowledgment (2/2) Hardware Status After Reset Serial interface UART6 Receive buffer register 6 (RXB6) Transmit buffer register 6 (TXB6) Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) Asynchronous serial interface transmission error status register 6 (ASIF6)

  • Page 244: Register For Confirming Reset Source

    CHAPTER 14 RESET FUNCTION 14.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0S/KA1+. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.

  • Page 245: Chapter 15 Power-on-clear Circuit

    CHAPTER 15 POWER-ON-CLEAR CIRCUIT 15.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. • Generates internal reset signal at power on. • Compares supply voltage (V = 2.1 V ±0.1 V), and generates internal reset signal ) and detection voltage (V when V <...

  • Page 246: Configuration Of Power-on-clear Circuit

    CHAPTER 15 POWER-ON-CLEAR CIRCUIT 15.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 15-1. Figure 15-1. Block Diagram of Power-on-Clear Circuit Internal reset signal − Reference voltage source 15.3 Operation of Power-on-Clear Circuit = 2.1 V ±0.1 V) are compared, In the power-on-clear circuit, the supply voltage (V ) and detection voltage (V...

  • Page 247: Cautions For Power-on-clear Circuit

    CHAPTER 15 POWER-ON-CLEAR CIRCUIT 15.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POC detection voltage (V ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.

  • Page 248

    CHAPTER 15 POWER-ON-CLEAR CIRCUIT Figure 15-3. Example of Software Processing After Release of Reset (2/2) • Checking reset cause Check reset source WDTRF of RESF register = 1? Reset processing by watchdog timer LVIRF of RESF register = 1? Reset processing by low-voltage detector Power-on clear/external reset generated...

  • Page 249: Chapter 16 Low-voltage Detector

    CHAPTER 16 LOW-VOLTAGE DETECTOR 16.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has following functions. • Compares supply voltage (V ) and detection voltage (V ), and generates an internal interrupt signal or internal reset signal when V < V •...

  • Page 250: Registers Controlling Low-voltage Detector

    CHAPTER 16 LOW-VOLTAGE DETECTOR 16.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. • Low-voltage detect register (LVIM) • Low-voltage detection level select register (LVIS) (1) Low-voltage detect register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 251

    CHAPTER 16 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level select register (LVIS) This register selects the low-voltage detection level. This register can be set by an 8-bit memory manipulation instruction. Note Reset input clears this register to 00H Figure 16-3. Format of Low-Voltage Detection Level Select Register (LVIS) Note Address: FF51H, After reset: 00H Symbol...

  • Page 252: Operation Of Low-voltage Detector

    CHAPTER 16 LOW-VOLTAGE DETECTOR 16.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. • Used as reset Compares the supply voltage (V ) and detection voltage (V ), and generates an internal reset signal when <...

  • Page 253

    CHAPTER 16 LOW-VOLTAGE DETECTOR Figure 16-4. Timing of Low-Voltage Detector Internal Reset Signal Generation Supply voltage (V LVI detection voltage POC detection voltage <2> Time LVIMK flag (set by software) <1> Note 1 LVION flag Not cleared Not cleared (set by software) <3>...

  • Page 254

    CHAPTER 16 LOW-VOLTAGE DETECTOR (2) When used as interrupt • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select register (LVIS).

  • Page 255

    CHAPTER 16 LOW-VOLTAGE DETECTOR Figure 16-5. Timing of Low-Voltage Detector Interrupt Signal Generation Supply voltage (V LVI detection voltage POC detection voltage Time <2> LVIMK flag (set by software) <1> Note 1 <7> Cleared by software LVION flag (set by software) <3>...

  • Page 256: Cautions For Low-voltage Detector

    CHAPTER 16 LOW-VOLTAGE DETECTOR 16.5 Cautions for Low-Voltage Detector In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVI detection voltage ), the operation is as follows depending on how the low-voltage detector is used. <1>...

  • Page 257

    CHAPTER 16 LOW-VOLTAGE DETECTOR Figure 16-6. Example of Software Processing After Release of Reset (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset Note ; Check reset source Initialization Initialization of ports processing <1>...

  • Page 258

    CHAPTER 16 LOW-VOLTAGE DETECTOR Figure 16-6. Example of Software Processing After Release of Reset (2/2) • Checking reset source Check reset source WDTRF of RESF register = 1? Reset processing by watchdog timer LVIRF of RESF register = 1? Power-on-clear/external reset generated Reset processing by low-voltage detector...

  • Page 259: Chapter 17 Option Byte

    CHAPTER 17 OPTION BYTE 17.1 Functions of Option Byte The address 0080H of the flash memory of the 78K0S/KA1+ is an option byte area. When power is supplied or when starting after a reset, the option byte is automatically referenced, and settings for the specified functions are performed.

  • Page 260: Format Of Option Byte

    CHAPTER 17 OPTION BYTE 17.2 Format of Option Byte Format of option bytes is shown below. Figure 17-2. Format of Option Byte (1/2) Address: 0080H DEFOSTS1 DEFOSTS0 RMCE OSCSEL1 OSCSEL0 LIOCP DEFOSTS1 DEFOSTS0 Oscillation stabilization time on power application or after reset release µ...

  • Page 261

    CHAPTER 17 OPTION BYTE Figure 17-2. Format of Option Byte (2/2) LIOCP Low-speed internal oscillates Cannot be stopped (oscillation does not stop even if 1 is written to the LSRSTOP bit) Can be stopped by software (oscillation stops when 1 is written to the LSRSTOP bit) Cautions 1.

  • Page 262: Chapter 18 Flash Memory

    CHAPTER 18 FLASH MEMORY 18.1 Features The internal flash memory of the 78K0S/KA1+ has the following features. Erase/write even without preparing a separate dedicated power supply Capacity: 2 KB/4 KB • Erase unit: 1 block (256 bytes) • Write unit: 1 block (at onboard/offboard programming time), 1 byte (at self programming time) Rewriting method •...

  • Page 263: Memory Configuration

    CHAPTER 18 FLASH MEMORY 18.2 Memory Configuration The 2/4 KB internal flash memory area is divided into 8/16 blocks and can be programmed/erased in block units. All the blocks can also be erased at once, by using a dedicated flash programmer. Figure 18-1.

  • Page 264

    CHAPTER 18 FLASH MEMORY 18.3 Functional Outline The internal flash memory of the 78K0S/KA1+ can be rewritten by using the rewrite function of the dedicated flash programmer, regardless of whether the 78K0S/KA1+ has already been mounted on the target system or not (on- board/off-board programming).

  • Page 265: Writing With Flash Programmer

    CHAPTER 18 FLASH MEMORY 18.4 Writing with Flash Programmer The following two types of dedicated flash programmers can be used for writing data to the internal flash memory of the 78K0S/KA1+. • FlashPro4 (PG-FP4, FL-PR4) • PG-FPL2 Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) On-board programming The contents of the flash memory can be rewritten after the 78K0S/KA1+ has been mounted on the target system.

  • Page 266: Programming Environment

    CHAPTER 18 FLASH MEMORY 18.5 Programming Environment The environment required for writing a program to the flash memory is illustrated below. Figure 18-2. Environment for Writing Program to Flash Memory (FlashPro4) FlashPro4 RESET RS-232-C Axxxx Bxxxxx Cxxxxxx SI/RxD STATVE PG-FP4 SO/TxD 78K0S/KA1+ Host machine...

  • Page 267

    CHAPTER 18 FLASH MEMORY Table 18-2. Wiring Between 78K0S/KA1+ and FlashPro4 FlashPro4 Connection Pin 78K0S/KA1+ Connection Pin Pin Name Pin Function Pin Name Pin No. Note Output Clock to 78K0S/KA1+ X1/P121 Note FLMD0 Output On-board mode signal Note SI/RxD Input Receive signal X2/P122 Note...

  • Page 268: Pin Connection On Board

    CHAPTER 18 FLASH MEMORY 18.6 Pin Connection on Board To write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.

  • Page 269: Reset Pin

    CHAPTER 18 FLASH MEMORY Figure 18-7. PG-FP4 GUI Software Setting Example Set oscillation frequency Click (Standard tab in Device setup window) (Main window) Table 18-5. Oscillation Frequency and PG-FP4 GUI Software Setting Value Example Oscillation Frequency PG-FP4 GUI Software Setting Value Example (Communication Frequency) 1 MHz ≤...

  • Page 270: Port Pins

    CHAPTER 18 FLASH MEMORY Figure 18-8. Signal Collision (RESET Pin) 78K0S/KA1+ Dedicated flash programmer Signal collision connection signal RESET Reset signal generator Output pin In the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash programmer.

  • Page 271: On-board And Off-board Flash Memory Programming

    CHAPTER 18 FLASH MEMORY 18.7 On-Board and Off-Board Flash Memory Programming 18.7.1 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash programmer, set the 78K0S/KA1+ in the flash memory programming mode. When the 78K0S/KA1+ is connected to the flash programmer and a communication command is transmitted to the microcontroller, the microcontroller is set in the flash memory programming mode.

  • Page 272: Security Settings

    CHAPTER 18 FLASH MEMORY Table 18-7. Response Name Response Name Function Acknowledges command/data. Acknowledges illegal command/data. 18.7.3 Security settings The operations shown below can be prohibited using the security setting command. • Batch erase (chip erase) is prohibited Execution of the block erase and batch erase (chip erase) commands for entire blocks in the flash memory is prohibited.

  • Page 273: Flash Memory Programming By Self Writing

    CHAPTER 18 FLASH MEMORY Table 18-9 shows the relationship between the security setting and the operation in each programming mode. Table 18-9. Relationship Between Security Setting and Operation In Each Programming Mode Programming Mode On-Board/Off-Board Programming Self Programming Security Setting Security Setting Security Operation Security Setting...

  • Page 274

    Figure 18-10. Block Diagram of Self Programming Internal bus Flash programming command Protect byte register (FLCMD) Flash programming mode Flash protect command PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 FLCMD2 FLCMD1 FLCMD0 Self programming mode control register (FLPMC) register (PFCMD) setting sequencer Self programming mode setting register HALT signal Self programming command execution...

  • Page 275

    CHAPTER 18 FLASH MEMORY Figure 18-11. Self Programming State Transition Diagram User program Operation setting Normal mode Specific sequence Operation setting Register for Self programming mode self programming Self programming command Self programming execution by HALT instruction command completion/error Flash memory control block (hardware) Operation reference Self programming...

  • Page 276: Cautions On Self Programming Function

    CHAPTER 18 FLASH MEMORY 18.8.2 Cautions on self programming function • No instructions can be executed while a self programming command is being executed. Therefore, clear and restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self programming.

  • Page 277

    CHAPTER 18 FLASH MEMORY Figure 18-12. Format of Flash Programming Mode Control Register (FLPMC) Note 1 Note 2 Address: FFA2H After reset: Undefined Symbol FLPMC PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 FLSPM FLSPM Selection of operation mode during self programming mode Normal mode Flash memory instructions can be fetched from all addresses.

  • Page 278

    CHAPTER 18 FLASH MEMORY Figure 18-13. Format of Flash Protect Command Register (PFCMD) Address: FFA0H After reset: Undefined Symbol PFCMD REG7 REG6 REG5 REG4 REG3 REG2 REG1 REG0 (3) Flash status register (PFS) If data is not written to the flash programming mode control register (FLPMC), which is protected, in the correct sequence (writing the flash protect command register (PFCMD)), FLPMC is not written and a protection error occurs.

  • Page 279

    CHAPTER 18 FLASH MEMORY If VCERR is set, it means that the flash memory has not been erased or written correctly. Erase or write the memory again in the specified procedure. Remark The VCERR flag may also be set if an erase or write protect error occurs. <Reset conditions>...

  • Page 280

    CHAPTER 18 FLASH MEMORY Figure 18-15. Format of Flash Programming Command Register (FLCMD) Address: FFA3H After reset: 00H Symbol FLCMD FLCMD2 FLCMD1 FLCMD0 FLCMD2 FLCMD1 FLCMD0 Command Name Function Internal verify This command is used to check if data has been correctly written to the flash memory.

  • Page 281

    CHAPTER 18 FLASH MEMORY Figure 18-16. Format of Flash Address Pointer H/L (FLAPH/FLAPL) Address: FFA4H, FFA5H After reset: Undefined FLAPH (FFA5H) FLAPL (FFA4H) Caution Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address pointer H compare register (FLAPHC) to 0 before executing the self programming command.

  • Page 282

    CHAPTER 18 FLASH MEMORY (7) Flash write buffer register (FLW) This register is used to store the data to be written to the flash memory. This register is set with a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 18-18.

  • Page 283

    CHAPTER 18 FLASH MEMORY Figure 18-19. Format of Protect Byte Address: 0081H PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 µ • PD78F9221 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 Status Blocks 7 to 0 are protected. Blocks 5 to 0 are protected. Blocks 6 and 7 can be written or erased. Blocks 3 to 0 are protected.

  • Page 284: Example Of Shifting Normal Mode To Self Programming Mode

    CHAPTER 18 FLASH MEMORY 18.8.4 Example of shifting normal mode to self programming mode The operating mode must be shifted from normal mode to self programming mode before performing self programming. An example of shifting to self programming mode is explained below. <1>...

  • Page 285

    CHAPTER 18 FLASH MEMORY Figure 18-20. Example of Shifting to Self Programming Mode Shift to self programming mode <1> Disable interrupts (by setting MK0 and MK1 to FFH and executing ; When interrupt function is used DI instruction) <2> Clear PFS PFCMD = A5H FLPMC = 01H (set value) ;...

  • Page 286

    CHAPTER 18 FLASH MEMORY An example of the program that shifts the mode to self programming mode is shown below. ;---------------------------- ;START ;---------------------------- MK0,#11111111B ; Masks all interrupts MK1,#11111111B ModeOnLoop: PFS,#00H ; Clears flash status register PFCMD,#0A5H ; PFCMD register control FLPMC,#01H ;...

  • Page 287: Example Of Shifting Self Programming Mode To Normal Mode

    CHAPTER 18 FLASH MEMORY 18.8.5 Example of shifting self programming mode to normal mode The operating mode must be returned from self programming mode to normal mode after performing self programming. An example of shifting to normal mode is explained below. <1>...

  • Page 288

    CHAPTER 18 FLASH MEMORY Figure 18-21. Example of Shifting to Normal Mode Shift to normal mode <1> Clear PFS PFCMD = A5H FLPMC = 00H (set value) ; Set value is invalid <2> FLPMC = 0FFH (inverted set value) ; Set value is valid FLPMC = 00H (set value) Abnormal <3>...

  • Page 289

    CHAPTER 18 FLASH MEMORY An example of a program that shifts the mode to normal mode is shown below. ;---------------------------- ;START ;---------------------------- ModeOffLoop: PFS,#00H ; Clears flash status register PFCMD,#0A5H ; PFCMD register control FLPMC,#00H ; FLPMC register control (sets value) FLPMC,#0FFH ;...

  • Page 290: Example Of Block Erase Operation In Self Programming Mode

    CHAPTER 18 FLASH MEMORY 18.8.6 Example of block erase operation in self programming mode An example of the block erase operation in self programming mode is explained below. <1> Set 03H (block erase) to the flash program command register (FLCMD). <2>...

  • Page 291

    CHAPTER 18 FLASH MEMORY Figure 18-22. Example of Block Erase Operation in Self Programming Mode Block erasure <1> Set erase command (FLCMD = 03H) <2> Set no. of block to be erased to FLAPH <3> Set FLAPL to 00H <4> Set the same value as that of FLAPH to FLAPHC <5>...

  • Page 292

    CHAPTER 18 FLASH MEMORY An example of a program that performs a block erase in self programming mode is shown below. ;---------------------------- ;START ;---------------------------- FlashBlockErase: FLCMD,#03H ; Sets flash control command (block erase) FLAPH,#07H ; Sets number of block to be erased (block 7 is specified here) FLAPL,#00H ;...

  • Page 293: Example Of Block Blank Check Operation In Self Programming Mode

    CHAPTER 18 FLASH MEMORY 18.8.7 Example of block blank check operation in self programming mode An example of the block blank check operation in self programming mode is explained below. <1> Set 04H (block blank check) to the flash program command register (FLCMD). <2>...

  • Page 294

    CHAPTER 18 FLASH MEMORY Figure 18-23. Example of Block Blank Check Operation in Self Programming Mode Block blank check <1> Set block blank check command (FLCMD = 04H) <2> Set no. of block for blank check to FLAPH <3> Set FLAPL to 00H <4>...

  • Page 295

    CHAPTER 18 FLASH MEMORY An example of a program that performs a block blank check in self programming mode is shown below. ;---------------------------- ;START ;---------------------------- FlashBlockBlankCheck: FLCMD,#04H ; Sets flash control command (block blank check) FLAPH,#07H ; Sets number of block for blank check (block 7 is specified ;...

  • Page 296: Example Of Byte Write Operation In Self Programming Mode

    CHAPTER 18 FLASH MEMORY 18.8.8 Example of byte write operation in self programming mode An example of the byte write operation in self programming mode is explained below. <1> Set 05H (byte write) to the flash program command register (FLCMD). <2>...

  • Page 297

    CHAPTER 18 FLASH MEMORY Figure 18-24. Example of Byte Write Operation in Self Programming Mode Byte write <1> Set byte write command (FLCMD = 05H) <2> Set no. of block to be written, to FLAPH <3> Set address at which data is to be written, to FLAPL <4>...

  • Page 298

    CHAPTER 18 FLASH MEMORY An example of a program that performs a byte write in self programming mode is shown below. ;---------------------------- ;START ;---------------------------- FlashWrite: FLCMD,#05H ; Sets flash control command (byte write) FLAPH,#07H ; Sets address to which data is to be written, with ;...

  • Page 299: Example Of Internal Verify Operation In Self Programming Mode

    CHAPTER 18 FLASH MEMORY 18.8.9 Example of internal verify operation in self programming mode An example of the internal verify operation in self programming mode is explained below. <1> Set 01H (internal verify) to the flash program command register (FLCMD). <2>...

  • Page 300

    CHAPTER 18 FLASH MEMORY Figure 18-25. Example of Internal Verify Operation in Self Programming Mode Internal verify <1> Set internal verify command (FLCMD = 01H) <2> Set no. of block for internal verify, to FLAPH <3> Set start address to FLAPL <4>...

  • Page 301

    CHAPTER 18 FLASH MEMORY An example of a program that performs an internal verify in self programming mode is shown below. ;---------------------------- ;START ;---------------------------- FlashVerify: FLCMD,#01H ; Sets flash control command (internal verify) FLAPH,#07H ; Sets verify start address with FLAPH (block 7 is specified ;...

  • Page 302: Examples Of Operation When Command Execution Time Should Be Minimized In Self Programming Mode

    CHAPTER 18 FLASH MEMORY 18.8.10 Examples of operation when command execution time should be minimized in self programming mode Examples of operation when the command execution time should be minimized in self programming mode are explained below. (1) Erasure to blank check <1>...

  • Page 303

    CHAPTER 18 FLASH MEMORY An example of a program when the command execution time (from erasure to black check) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------- ;START ;--------------------------------------------------------------------- MK0,#11111111B ; Masks all interrupts MK1,#11111111B ModeOnLoop: PFS,#00H ;...

  • Page 304

    CHAPTER 18 FLASH MEMORY FLAPHC,#07H ; Sets blank check block compare number (same value as of ; FLAPH) FLAPLC,#0FFH ; Fixes FLAPLC to “FFH” WDTE,#0ACH ; Clears & restarts WDT HALT ; Self programming is started A,PFS A,#00H $StatusError ; Checks blank check error ;...

  • Page 305

    CHAPTER 18 FLASH MEMORY (2) Write to internal verify <1> Mode is shifted from normal mode to self programming mode (<1> to <5> in 18.8.4) <2> Specification of source data for write <3> Execution of byte write → Error check (<1> to <10> in 18.8.8) <4>...

  • Page 306

    CHAPTER 18 FLASH MEMORY An example of a program when the command execution time (from write to internal verify) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------- ;START ;--------------------------------------------------------------------- MK0,#11111111B ; Masks all interrupts MK1,#11111111B ModeOnLoop: PFS,#00H ;...

  • Page 307

    CHAPTER 18 FLASH MEMORY INCW ; Address at which data is to be written + 1 FlashWriteLoop FlashVerify: MOVW HL,#WriteAdr ; Sets verify address FLCMD,#01H ; Sets flash control command (internal verify) FLAPH,A ; Sets verify start address FLAPL,A ; Sets verify start address FLAPHC,A ;...

  • Page 308

    CHAPTER 18 FLASH MEMORY normal mode in order to return to normal processing ;--------------------------------------------------------------------- StatusError: ;--------------------------------------------------------------------- ;END (normal termination processing) ;--------------------------------------------------------------------- StatusNormal: ;--------------------------------------------------------------------- ; Data to be written ;--------------------------------------------------------------------- DataAdrTop: DataAdrBtm: ;--------------------------------------------------------------------- User’s Manual U16898EJ3V0UD...

  • Page 309: Examples Of Operation When Interrupt-disabled Time Should Be Minimized In Self Programming Mode

    CHAPTER 18 FLASH MEMORY 18.8.11 Examples of operation when interrupt-disabled time should be minimized in self programming mode Examples of operation when the interrupt-disabled time should be minimized in self programming mode are explained below. (1) Erasure to blank check <1>...

  • Page 310

    CHAPTER 18 FLASH MEMORY Figure 18-28. Example of Operation When Interrupt-Disabled Time Should Be Minimized (from Erasure to Blank Check) Erasure to blank check Figure 18-22 <1> Specify block erase command <1> to <5> <2> Shift to self programming Figure 18-20 mode <1>...

  • Page 311

    CHAPTER 18 FLASH MEMORY An example of a program when the interrupt-disabled time (from erasure to blank check) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------- ;START ;--------------------------------------------------------------------- FlashBlockErase: ; Sets erase command FLCMD,#03H ; Sets flash control command (block erase) FLAPH,#07H ;...

  • Page 312

    CHAPTER 18 FLASH MEMORY CALL !ModeOff ; Shift to normal mode StatusNormal ;--------------------------------------------------------------------- ;END (abnormal termination processing); Perform processing to shift to normal mode in order to return to normal processing ;--------------------------------------------------------------------- StatusError: ;--------------------------------------------------------------------- ;END (normal termination processing) ;--------------------------------------------------------------------- StatusNormal: ;--------------------------------------------------------------------- ;Processing to shift to self programming mode ;---------------------------------------------------------------------...

  • Page 313

    CHAPTER 18 FLASH MEMORY FLPMC,#0FFH ; FLPMC register control (inverts set value) FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value) A,PFS A,#00H $ModeOff ; Checks completion of write to specific registers ; Repeats the same processing when an error occurs MK0,#INT_MK0 ;...

  • Page 314

    CHAPTER 18 FLASH MEMORY (2) Write to internal verify <1> Specification of source data for write <2> Specification of byte write command (<1> to <4> in 18.8.8) <3> Mode is shifted from normal mode to self programming mode (<1> to <5> in 18.8.4) <4>...

  • Page 315

    CHAPTER 18 FLASH MEMORY Figure 18-29. Example of Operation When Interrupt-Disabled Time Should Be Minimized (from Write to Internal Verify) Write to internal verify <1> Set source data for write Figure 18-24 <2> Specify byte write command <1> to <4> <3>...

  • Page 316

    CHAPTER 18 FLASH MEMORY An example of a program when the interrupt-disabled time (from write to internal verify) should be minimized in self programming mode is shown below. ;--------------------------------------------------------------------- ;START ;--------------------------------------------------------------------- ; Sets write command FlashWrite: MOVW HL,#DataAdrTop ; Sets address at which data to be written is located MOVW DE,#WriteAdr ;...

  • Page 317

    CHAPTER 18 FLASH MEMORY ; Setting internal verify command FlashVerify: MOVW HL,#WriteAdr ; Sets verify address FLCMD,#01H ; Sets flash control command (internal verify) FLAPH,A ; Sets verify start address FLAPL,A ; Sets verify start address FLAPHC,A ; Sets verify end address FLAPLC,A ;...

  • Page 318

    CHAPTER 18 FLASH MEMORY ModeOnLoop: PFS,#00H ; Clears flash status register PFCMD,#0A5H ; PFCMD register control FLPMC,#01H ; FLPMC register control (sets value) FLPMC,#0FEH ; FLPMC register control (inverts set value) FLPMC,#01H ; Sets self programming mode via FLPMC register control (sets ;...

  • Page 319

    CHAPTER 18 FLASH MEMORY DataAdrBtm: ;--------------------------------------------------------------------- User’s Manual U16898EJ3V0UD...

  • Page 320: Chapter 19 Instruction Set Overview

    CHAPTER 19 INSTRUCTION SET OVERVIEW This chapter lists the instruction set of the 78K0S/KA1+. For details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E). 19.1 Operation 19.1.1 Operand identifiers and description methods Operands are described in “Operand”...

  • Page 321: Description Of "operation" Column

    CHAPTER 19 INSTRUCTION SET OVERVIEW 19.1.2 Description of “Operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...

  • Page 322: Operation List

    CHAPTER 19 INSTRUCTION SET OVERVIEW 19.2 Operation List Mnemonic Operand Bytes Clocks Operation Flag AC CY r ← byte r, #byte saddr, #byte (saddr) ← byte sfr, #byte sfr ← byte Note A, r A ← r Note r, A r ←...

  • Page 323

    CHAPTER 19 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag AC CY MOVW rp, #word rp ← word AX ← (saddrp) AX, saddrp (saddrp) ← AX saddrp, AX Note AX ← rp AX, rp Note rp, AX rp ← AX Note XCHW AX, rp...

  • Page 324

    CHAPTER 19 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag AC CY SUBC A, #byte A, CY ← A − byte − CY × × × (saddr), CY ← (saddr) − byte − CY × × × saddr, #byte A, CY ←...

  • Page 325

    CHAPTER 19 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag AC CY A, #byte A − byte × × × (saddr) − byte × × × saddr, #byte A − r × × × A, r A − (saddr) ×...

  • Page 326

    CHAPTER 19 INSTRUCTION SET OVERVIEW Mnemonic Operand Bytes Clocks Operation Flag AC CY CALL !addr16 (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) PC ← addr16, SP ← SP − 2 (SP − 1) ← (PC + 1) , (SP −...

  • Page 327: Instructions Listed By Addressing Type

    CHAPTER 19 INSTRUCTION SET OVERVIEW 19.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte saddr !addr16 [DE] [HL] $addr16 None [HL + byte]...

  • Page 328

    CHAPTER 19 INSTRUCTION SET OVERVIEW (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note 2nd Operand #word saddrp None 1st Operand ADDW SUBW MOVW MOVW MOVW CMPW XCHW Note MOVW MOVW INCW DECW PUSH saddrp MOVW MOVW Note Only when rp = BC, DE, or HL.

  • Page 329

    CHAPTER 19 INSTRUCTION SET OVERVIEW (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand !addr16 [addr5] $addr16 1st Operand Basic instructions CALL CALLT Compound instructions DBNZ (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP User’s Manual U16898EJ3V0UD...

  • Page 330: Chapter 20 Electrical Specifications ((t) Product, (s) Product, (r) Product, (a) Product

    CHAPTER 20 ELECTRICAL SPECIFICATIONS ((T) product, (S) product, (R) product, (A) product) Caution For (A) products, the specifications are target values, and may change after device evaluation. Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit −0.3 to +6.5 Supply voltage −0.3 to +0.3 Note...

  • Page 331

    CHAPTER 20 ELECTRICAL SPECIFICATIONS ((T) product, (S) product, (R) product, (A) product) − °C (T), (S), (R), (A) product T 40 to Note 1 = −40 to +85°C, V X1 Oscillator Characteristics (T = 2.0 to 5.5 V = 0 V) Resonator Recommended Circuit Parameter Conditions...

  • Page 332

    CHAPTER 20 ELECTRICAL SPECIFICATIONS ((T) product, (S) product, (R) product, (A) product) − °C (T), (S), (R), (A) product T 40 to Note 1 = −40 to +85°C, V High-Speed Internal Oscillator Characteristics (T = 2.0 to 5.5 V = 0 V) Resonator Parameter Conditions...

  • Page 333

    CHAPTER 20 ELECTRICAL SPECIFICATIONS ((T) product, (S) product, (R) product, (A) product) − °C (T), (S), (R), (A) product T 40 to Note = −40 to +85°C, V DC Characteristics (T = 2.0 to 5.5 V = 0 V) (1/2) Parameter Symbol Conditions...

  • Page 334

    CHAPTER 20 ELECTRICAL SPECIFICATIONS ((T) product, (S) product, (R) product, (A) product) − °C (T), (S), (R), (A) product T 40 to Note 1 DC Characteristics (T = −40 to +85°C, V = 2.0 to 5.5 V = 0 V) (2/2) Parameter Symbol Conditions...

  • Page 335

    CHAPTER 20 ELECTRICAL SPECIFICATIONS ((T) product, (S) product, (R) product, (A) product) − °C (T), (S), (R), (A) product T 40 to AC Characteristics Note 1 (1) Basic operation (T = −40 to +85°C, V = 2.0 to 5.5 V = 0 V) Parameter Symbol...

  • Page 336

    CHAPTER 20 ELECTRICAL SPECIFICATIONS ((T) product, (S) product, (R) product, (A) product) − °C (T), (S), (R), (A) product T 40 to vs. V (Crystal/Ceramic Oscillation Clock, External Clock Input) Guaranteed operation range 0.33 Supply voltage V vs. V (High-speed internal ocillator Clock) 4.22 Guaranteed operation range...

  • Page 337

    CHAPTER 20 ELECTRICAL SPECIFICATIONS ((T) product, (S) product, (R) product, (A) product) − °C (T), (S), (R), (A) product T 40 to Note = −40 to +85°C, V (2) Serial interface (T = 2.0 to 5.5 V = 0 V) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol...

  • Page 338

    CHAPTER 20 ELECTRICAL SPECIFICATIONS ((T) product, (S) product, (R) product, (A) product) − °C (T), (S), (R), (A) product T 40 to Note 1 A/D Converter Characteristics (T = −40 to +85°C, 2.7 V ≤ AV ≤ V ≤ 5.5 V, V = 0 V Parameter Symbol...

  • Page 339

    CHAPTER 20 ELECTRICAL SPECIFICATIONS ((T) product, (S) product, (R) product, (A) product) − °C (T), (S), (R), (A) product T 40 to POC Circuit Characteristics (T = −40 to +85°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage µ Power supply boot time : 0 V →...

  • Page 340

    CHAPTER 20 ELECTRICAL SPECIFICATIONS ((T) product, (S) product, (R) product, (A) product) − °C (T), (S), (R), (A) product T 40 to = −40 to +85°C) LVI Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage LVI0 LVI1 LVI2 LVI3...

  • Page 341

    CHAPTER 20 ELECTRICAL SPECIFICATIONS ((T) product, (S) product, (R) product, (A) product) − °C (T), (S), (R), (A) product T 40 to Flash Memory Programming Characteristics (T = –40 to +85°C, 2.7 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions...

  • Page 342: Chapter 21 Electrical Specifications (target Values) ((t2) Product)

    CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((T2) product) Caution These specifications show target values, which may change after device evaluation. The operating voltage range may also change. Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit −0.3 to +6.5 Supply voltage −0.3 to +0.3 Note...

  • Page 343

    CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((T2) product) − °C (T2) product T 40 to Notes 2. This varies depending on the allowable total loss (see the figure below). +120 Temperature [˚C] +125 Use the following formula to perform design such that the sum of the power consumption of the device is less than or equal to the total loss P (use at 80% or less of the rated value is recommended).

  • Page 344

    CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((T2) product) − °C (T2) product T 40 to Note 1 = −40 to +125°C, V X1 Oscillator Characteristics (T = 2.0 to 5.5 V = 0 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP.

  • Page 345

    CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((T2) product) − °C (T2) product T 40 to Note 1 = −40 to +125°C, V High-Speed Internal Oscillator Characteristics (T = 2.0 to 5.5 V = 0 V) Resonator Parameter Conditions MIN. TYP. MAX.

  • Page 346

    CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((T2) product) − °C (T2) product T 40 to Note = −40 to +125°C, V DC Characteristics (T = 2.0 to 5.5 V = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output current, high Pins other than Per pin...

  • Page 347

    CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((T2) product) − °C (T2) product T 40 to Note 1 DC Characteristics (T = −40 to +125°C, V = 2.0 to 5.5 V = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 3 Supply Crystal/ceramic...

  • Page 348

    CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((T2) product) − °C (T2) product T 40 to AC Characteristics Note 1 (1) Basic operation (T = −40 to +125°C, V = 2.0 to 5.5 V = 0 V) Parameter Symbol Conditions MIN. TYP.

  • Page 349

    CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((T2) product) − °C (T2) product T 40 to vs. V (Crystal/Ceramic Oscillation Clock, External Clock Input) Guaranteed operation range 0.33 0.25 Supply voltage V vs. V (High-speed internal ocillator Clock) 4.22 Guaranteed operation range 0.95 0.47 0.23...

  • Page 350

    CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((T2) product) − °C (T2) product T 40 to Note = −40 to +125°C, V (2) Serial interface (T = 2.0 to 5.5 V = 0 V) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions...

  • Page 351

    CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((T2) product) − °C (T2) product T 40 to Note 1 A/D Converter Characteristics (T = −40 to +125°C, 2.7 V ≤ AV ≤ V ≤ 5.5 V, V = 0 V Parameter Symbol Conditions MIN.

  • Page 352

    CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((T2) product) − °C (T2) product T 40 to POC Circuit Characteristics (T = −40 to +125°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit 2.26 Detection voltage µ Power supply boot time : 0 V → 2.1 V Note 1 Response delay time 1 When power supply rises, after reaching...

  • Page 353

    CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((T2) product) − °C (T2) product T 40 to = −40 to +125°C) LVI Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage 4.65 LVI0 4.45 LVI1 4.25 LVI2 4.05 LVI3 3.85 LVI4 3.15...

  • Page 354

    CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((T2) product) − °C (T2) product T 40 to Flash Memory Programming Characteristics (T = –40 to +105°C, 2.7 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX.

  • Page 355

    CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((T2) product) − °C (T2) product T 40 to Note 3. When guaranteeing the flash self programming, use the following formula to perform design such that the sum of the power consumption of the device is less than or equal to the total loss P (use at 80% or less of the rated value is recommended).

  • Page 356: Chapter 22 Electrical Specifications (target Values) ((a2) Product)

    CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((A2) product) Caution These specifications show target values, which may change after device evaluation. The operating voltage range may also change. Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit −0.3 to +6.5 Supply voltage −0.3 to +0.3 Note...

  • Page 357

    CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((A2) product) − °C (A2) product T 40 to Notes 2. This varies depending on the allowable total loss (see the figure below). +120 Temperature [˚C] +125 Use the following formula to perform design such that the sum of the power consumption of the device is less than or equal to the total loss P (use at 80% or less of the rated value is recommended).

  • Page 358

    CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((A2) product) − °C (A2) product T 40 to Note 1 = −40 to +125°C, V X1 Oscillator Characteristics (T = 2.0 to 5.5 V = 0 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP.

  • Page 359

    CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((A2) product) − °C (A2) product T 40 to Note 1 = −40 to +125°C, V High-Speed Internal Oscillator Characteristics (T = 2.0 to 5.5 V = 0 V) Resonator Parameter Conditions MIN. TYP. MAX.

  • Page 360

    CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((A2) product) − °C (A2) product T 40 to Note = −40 to +125°C, V DC Characteristics (T = 2.0 to 5.5 V = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output current, high Pins other than Per pin...

  • Page 361

    CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((A2) product) − °C (A2) product T 40 to Note 1 DC Characteristics (T = −40 to +125°C, V = 2.0 to 5.5 V = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 3 Supply Crystal/ceramic...

  • Page 362

    CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((A2) product) − °C (A2) product T 40 to AC Characteristics Note 1 (1) Basic operation (T = −40 to +125°C, V = 2.0 to 5.5 V = 0 V) Parameter Symbol Conditions MIN. TYP.

  • Page 363

    CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((A2) product) − °C (A2) product T 40 to vs. V (Crystal/Ceramic Oscillation Clock, External Clock Input) Guaranteed operation range 0.33 0.25 Supply voltage V vs. V (High-speed internal ocillator Clock) 4.22 Guaranteed operation range 0.95 0.47 0.23...

  • Page 364

    CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((A2) product) − °C (A2) product T 40 to Note = −40 to +125°C, V (2) Serial interface (T = 2.0 to 5.5 V = 0 V) UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions...

  • Page 365

    CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((A2) product) − °C (A2) product T 40 to Note 1 A/D Converter Characteristics (T = −40 to +125°C, 2.7 V ≤ AV ≤ V ≤ 5.5 V, V = 0 V Parameter Symbol Conditions MIN.

  • Page 366

    CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((A2) product) − °C (A2) product T 40 to POC Circuit Characteristics (T = −40 to +125°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit 2.26 Detection voltage µ Power supply boot time : 0 V → 2.1 V Note 1 Response delay time 1 When power supply rises, after reaching...

  • Page 367

    CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((A2) product) − °C (A2) product T 40 to = −40 to +125°C) LVI Circuit Characteristics (T Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage 4.65 LVI0 4.45 LVI1 4.25 LVI2 4.05 LVI3 3.85 LVI4 3.15...

  • Page 368

    CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((A2) product) − °C (A2) product T 40 to Flash Memory Programming Characteristics (T = –40 to +105°C, 2.7 V ≤ V ≤ 5.5 V, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX.

  • Page 369

    CHAPTER 22 ELECTRICAL SPECIFICATIONS (TARGET VALUES) ((A2) product) − °C (A2) product T 40 to Note 3. When guaranteeing the flash self programming, use the following formula to perform design such that the sum of the power consumption of the device is less than or equal to the total loss P (use at 80% or less of the rated value is recommended).

  • Page 370: Chapter 23 Package Drawing

    CHAPTER 23 PACKAGE DRAWING 20-PIN PLASTIC SSOP (7.62 mm (300)) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.13 mm of 6.65±0.15 its true position (T.P.) at maximum material condition. 0.475 MAX. 0.65 (T.P.) +0.08 0.24 −0.07 0.1±0.05...

  • Page 371: Chapter 24 Package Marking Information

    CHAPTER 24 PACKAGE MARKING INFORMATION • 20-pin plastic SSOP (1) Blank products µ µ <1> PD78F9221 <2> PD78F9222 F9221 F9222 YWWP YWWP Note Note Leed-free mark Leed-free mark Index mark Index mark (2) Products for which writing has already been performed µ...

  • Page 372: Chapter 25 Recommended Soldering Conditions

    Cautions 1. Products whis –A at the end of the part number are lead-free products. 2. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Table 25-1. Surface Mounting Type Soldering Conditions (1/2)

  • Page 373

    Count: 3 times or less, Exposure limit: 7 days (after that, prebake at 125°C for 20 hours) Wave soldering For details, contact an NEC Electronics sales representative. − Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) −...

  • Page 374: Appendix A Development Tools

    APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the 78K0S/KA1+. Figure A-1 shows development tools. • Compatibility with PC98-NX series Unless stated otherwise, products which are supported by IBM PC/AT and compatibles can also be used with the PC98-NX series.

  • Page 375

    APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools (1/2) (1) When using the in-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A Software package • Software package Language processing software Debugging software • Assembler package • Integrated debugger • C compiler package • System simulator •...

  • Page 376

    APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools (2/2) (2) When using the in-circuit emulator QB-78K0SKX1MINI Software package • Software package Language processing software Debugging software • Assembler package • Integrated debugger • C compiler package • System simulator • Device file •...

  • Page 377: A.1 Software Package

    APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0S This is a package that bundles the software tools required for development of the 78K/0S Series. Software package The following tools are included. Note 1 Note 2 RA78K0S, CC78K0S, ID78K0S-NS, SM+ for 78K0S , SM78K0S , and device files.

  • Page 378: A.3 Control Software

    APPENDIX A DEVELOPMENT TOOLS Notes 2. CC78K0S-L is not included in the software package (SP78K0S). ×××× in the part number differs depending on the host machine and operating system to be used. Remark µ S××××RA78K0S µ S××××CC78K0S µ S××××CC78K0S-L ×××× Host Machine Supply Media AB17...

  • Page 379: A.5 Debugging Tools (hardware)

    APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) A.5.1 When using in-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A IE-78K0S-NS In-circuit emulator for debugging hardware and software of application system using 78K/0S In-circuit emulator Series. Supports integrated debugger (ID78K0S-NS). Used in combination with AC adapter, emulation probe, and interface adapter for connecting the host machine.

  • Page 380: A.6 Debugging Tools (software)

    APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) ID78K0S-NS This debugger supports the in-circuit emulators for the 78K/0S Series. ID78K0S-NS is Windows- (supporting in-circuit based software. emulator IE-78K0S-NS/ This debugger has enhanced debugging functions supporting C language. By using its window IE-78K0S-NS-A) integration function that associates the source program, disassemble display, and memory display Integrated debugger...

  • Page 381: Appendix B Notes On Target System Design

    APPENDIX B NOTES ON TARGET SYSTEM DESIGN The following show the conditions when connecting the emulation probe to the conversion connector and conversion socket in the case using in-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. Figure B-1.

  • Page 382

    APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B-2. Condition for Connecting Target System (When Using In-Circuit Emulator IE-78K0S-NS, IE-78K0S-NS-A) Emulation board IE-789234-NS-EM1 Emulation probe NP-30MC NP-30MC tip board Guide pin YQ-Guide 13 mm Conversion connector YSPACK30BK, NSPACK20BK 5 mm 15 mm 20 mm 37 mm...

  • Page 383: Appendix C Register Index

    APPENDIX C REGISTER INDEX C.1 Register Index (Register Name) 8-bit A/D conversion result register (ADCRH) … 164 8-bit compare register 80 (CR80) … 124 8-bit timer counter 80 (TM80) … 124 8-bit timer H compare register 01 (CMP01) … 131 8-bit timer H compare register 11 (CMP11) …...

  • Page 384

    APPENDIX C REGISTER INDEX Input switching control register (ISC) … 191 Interrupt mask flag register 0 (MK0) … 219 Interrupt mask flag register 1 (MK1) … 219 Interrupt request flag register 0 (IF0) … 218 Interrupt request flag register 1 (IF1) … 218 Low voltage detect register (LVIM) …...

  • Page 385: C.2 Register Index (symbol)

    APPENDIX C REGISTER INDEX C.2 Register Index (Symbol) ADCR: 10-bit A/D conversion result register … 163 ADCRH: 8-bit A/D conversion result register … 164 ADM: A/D converter mode register … 161 ADS: Analog input channel specify register … 163 ASICL6: Asynchronous serial interface control register 6 …...

  • Page 386

    APPENDIX C REGISTER INDEX OSTS: Oscillation stabilization time selection register … 71, 229 Port register 2 … 61 Port register 3 … 61 Port register 4 … 61 P12: Port register 12 … 61 P13: Port register 13 … 61 PCC: Processor clock control register …...

  • Page 387: Appendix D List Of Cautions

    APPENDIX D LIST OF CAUTIONS This appendix lists cautions described in this document. “Classification (hard/soft)” in table is as follows. Hard: Cautions for microcontroller internal/external hardware Soft: Cautions for software such as register settings or programs (1/17) Function Details of Cautions Page Function...

  • Page 388

    APPENDIX D LIST OF CAUTIONS (2/17) Function Details of Cautions Page Function Crystal/ − When using the crystal/ceramic oscillator, wire as follows in the area enclosed by p. 72 ceramic the broken lines in Figure 5-6 to avoid an adverse effect from wiring capacitance. oscillator •...

  • Page 389

    APPENDIX D LIST OF CAUTIONS (3/17) Function Details of Cautions Page Function 16-bit CR010: 16-bit If the register read period and the input of the capture trigger conflict when CR010 pp. 86, timer/ capture/ is used as a capture register, the capture trigger input takes precedence and the event compare read data is undefined.

  • Page 390

    APPENDIX D LIST OF CAUTIONS (4/17) Function Details of Cautions Page Function 16-bit PRM00: Always set data to PRM00 after stopping the timer operation. pp. 92, timer/ Prescaler mode event register 00 If the valid edge of the TI000 pin is to be set as the count clock, do not set the pp.

  • Page 391

    APPENDIX D LIST OF CAUTIONS (5/17) Function Details of Cautions Page Function 16-bit PPG output The cycle of the pulse generated through PPG output (CR000 setting value + 1) pp. 109, timer/ has a duty of (CR010 setting value + 1)/(CR000 setting value + 1). event One-shot pulse Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output.

  • Page 392

    APPENDIX D LIST OF CAUTIONS (6/17) Function Details of Cautions Page Function 8-bit timer CR80: compare When changing the value of CR80, be sure to stop the timer operation. If the p. 124 register 80 value of CR80 is changed with the timer operation enabled, a match interrupt request signal is generated immediately and the timer may be cleared.

  • Page 393

    APPENDIX D LIST OF CAUTIONS (7/17) Function Details of Cautions Page Function Watchdog WDTM: Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values. p. 148 timer Watchdog timer After reset is released, WDTM can be written only once by an 8-bit memory p.

  • Page 394

    APPENDIX D LIST OF CAUTIONS (8/17) Function Details of Cautions Page Function ADCR: 10-bit When writing to the A/D converter mode register (ADM) and analog input channel p. 163 Converter A/D conversion specification register (ADS), the contents of ADCR may become undefined. Read result register the conversion result following conversion completion before writing to ADM and ADS.

  • Page 395

    APPENDIX D LIST OF CAUTIONS (9/17) Function Details of Cautions Page Function ANI0/P20 to If a digital pulse is applied to the pins adjacent to the pins currently used for A/D p. 173 converter ANI3/P23 conversion, the expected value of the A/D conversion may not be obtained due to coupling noise.

  • Page 396

    APPENDIX D LIST OF CAUTIONS (10/17) Function Details of Cautions Page Function Serial TXB6: Transmit Do not refresh (write the same value to) TXB6 by software during a p. 182 interface buffer register 6 communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of UART6 asynchronous serial interface operation mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1).

  • Page 397

    APPENDIX D LIST OF CAUTIONS (11/17) Function Details of Cautions Page Function Serial ASICL6: Before setting the SBRT6 bit to 1, make sure that bit 7 (POWER6) and bit 5 p. 190 interface Asynchronous (RXE6) of ASIM6 = 1. Moreover, after setting the SBRT6 bit to 1, do not clear the UART6 serial interface SBRT6 bit to 0 before the SBF reception ends (an interrupt request signal is...

  • Page 398

    APPENDIX D LIST OF CAUTIONS (12/17) Function Details of Cautions Page Function Generation of Serial Keep the baud rate error during transmission to within the permissible error p. 209 serial clock interface range at the reception destination. UART6 Make sure that the baud rate error during reception satisfies the range shown in p.

  • Page 399

    APPENDIX D LIST OF CAUTIONS (13/17) Function Details of Cautions Page Function Standby OSTS: The wait time after the STOP mode is released does not include the time from the p. 229 function Oscillation release of the STOP mode to the start of clock oscillation (“a” in the figure below), stabilization regardless of whether STOP mode was released by reset signal generation or time select...

  • Page 400

    APPENDIX D LIST OF CAUTIONS (14/17) Function Details of Cautions Page Function Low- When used as <1> must always be executed. When LVIMK = 0, an interrupt may occur p. 252 voltage reset immediately after the processing in <3>. detector If supply voltage (V ) ≥...

  • Page 401

    APPENDIX D LIST OF CAUTIONS (15/17) Function Details of Cautions Page Function Security Flash After the security setting of the batch erase is set, erasure cannot be performed p. 272 settings for the device. In addition, even if a write command is executed, data different memory from that which has already been written to the flash memory cannot be written because the erase command is disabled.

  • Page 402

    APPENDIX D LIST OF CAUTIONS (16/17) Function Details of Cautions Page Function Flash FLAPHC, Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address p. 281 memory FLAPLC: Flash pointer H compare register (FLAPHC) to 0 before executing the self programming address pointer command.

  • Page 403

    372 nded products soldering − For soldering methods and conditions other than those recommended below, p. 372 conditions contact an NEC Electronics sales representative. Do not use different soldering methods together (except for partial heating). p. 372 User’s Manual U16898EJ3V0UD...

  • Page 404: E.1 Major Revisions In This Edition

    APPENDIX E REVISION HISTORY E.1 Major Revisions in This Edition (1/3) Page Description pp. 15, 18, 20 Modification of operating temperature range in CHAPTER 1 OVERVIEW p. 16 Addition of part number to 1.3 Ordering Information pp. 21, 22 Addition of Note to P34/RESET, P121/X1, and P122/X2 in 2.1 Pin Function List p.

  • Page 405

    APPENDIX E REVISION HISTORY (2/3) Page Description p. 117 Modification of <1> in (11) One-shot pulse output by software of 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 p. 118 Modification of <1> in (12) One-shot pulse output with external trigger of 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 p.

  • Page 406

    APPENDIX E REVISION HISTORY (3/3) Page Description p. 257 Modification of Figure 16-6. Example of Software Processing After Release of Reset (1/2) pp. 259, 260 Modification of description and configuration in CHAPTER 17 OPTION BYTE p. 259 Modification of Caution in Figure 17-2. Format of Option Byte (1/2) p.

  • Page 407: E.2 Revision History Up To Previous Editions

    APPENDIX E REVISION HISTORY E.2 Revision History up to Previous Editions The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters of each edition in which the revision was applied. (1/4) Edition Description Applied to: 2nd edition...

  • Page 408

    APPENDIX E REVISION HISTORY (2/4) Edition Description Applied to: Modification of output width of INTTM010 and INTTM000 in the following figures CHAPTER 6 16-BIT 2nd edition • Figure 6-17 CR010 Capture Operation with Rising Edge Specified TIMER/EVENT • Figure 6-20 Timing of Pulse Width Measurement Operation by Free-Running COUNTER 00 Counter and One Capture Register (with Both Edges Specified) •...

  • Page 409

    APPENDIX E REVISION HISTORY (3/4) Edition Description Applied to: CHAPTER 11 SERIAL 2nd edition Modification of 11.4.2 (2) (h) SBF transmission INTERFACE UART6 Modification of Table 11-4 Set Data of Baud Rate Generator Addition of Caution to and modification of Table 12-1 Interrupt Sources CHAPTER 12 INTERRUPT FUNCTIONS...

  • Page 410

    APPENDIX E REVISION HISTORY (4/4) Edition Description Applied to: APPENDIX A 2nd edition Modification Figure A-1 Development Tools DEVELOPMENT Modification of device file names and Remark in A.2 Language Processing Software TOOLS Addition of project manager name to A.3 Control Software Addition of PG-FPL2 to A.4 Flash Memory Writing Tools Modification of emulation board name used when the IE-78K0S-NS or IE-78K0S-NS-A is used, and deletion of NP-20GS and EV-9500GS-20, and addition of Specification of pin...

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