NEC PD703114 User Manual page 541

11.11 Operation Cautions
11.11.1 Stopping A/D conversion operation
If 0 is written in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register during A/D conversion, it stops
the A/D conversion operation and an A/D conversion result is not stored in the ADCR0m or ADCR1n register (m = 0 to
5, n = 0 to 7).
11.11.2 Trigger input during A/D conversion operation
If a trigger is input during A/D conversion, that trigger input is ignored.
11.11.3 External or timer trigger interval
Make the trigger interval (input time interval) in external or timer trigger mode longer than the conversion time
specified by the FR2 to FR0 bits of the ADSCM01 or ADSCM11 register.
(1) When interval = 0
If multiple triggers are input simultaneously, processing is performed assuming that they are one trigger
signal.
(2) When 0 < interval < conversion time
If an external or timer trigger is input during A/D conversion, that trigger input is ignored.
(3) When interval = conversion time
If an external or timer trigger is input at the same time as the end of A/D conversion (conflict of compare
termination signal and trigger), interrupt generation and storage of the value at which conversion ended in the
ADCR0m or ADCR1n register is performed correctly (m = 0 to 5, n = 0 to 7).
11.11.4 Operation in standby modes
(1) HALT mode
A/D conversion is suspended. If released by NMI or maskable interrupt input, the ADSCM00, ADSCM10,
ADSCM01, or ADSCM11 register and ADCR0m or ADCR1n register maintain their values (m = 0 to 5, n = 0
to 7).
If released by RESET input, the ADCR0m and ADCR1n registers are initialized.
(2) IDLE mode, software STOP mode
Since clock provision to A/D converter 0 or 1 stops, A/D conversion is not performed.
If released by NMI or maskable interrupt input, the ADSCM00, ADSCM10, ADSCM01, or ADSCM11 register
and ADCR0m or ADCR1n register maintain their values (m = 0 to 5, n = 0 to 7). However, if IDLE mode or
software STOP mode is set during an A/D conversion operation, the A/D conversion operation stops. If
released by RESET input, the ADCR0m and ADCR1n registers are initialized.
11.11.5 Compare match interrupt in timer trigger mode
The TM0n timer 0 register underflow interrupt (INTTM00 or INTTM01) and CM003 to CM005 or CM013 to CM015
match interrupt (INTCM003 to INTCM005 or INTCM013 to INTCM015) are A/D conversion start triggers that start a
conversion operation (n = 0,1). At this time, the CM003 to CM005 or CM013 to CM015 match interrupt (INTCM003 to
INTCM005 or INTCM013 to INTCM015) also functions as a compare register match interrupt for the CPU. In order
not to generate these match interrupts for the CPU, disable interrupts using the mask bits (TM0MK0, TM0MK1,
CM03MK0 to CM05MK0, CM03MK1 to CM05MK1) of the interrupt control registers (TM0IC0, TM0IC1, CM03IC0 to
CM05IC0, CM03IC1 to CM05IC1).
CHAPTER 11 A/D CONVERTER
User's Manual U15195EJ5V0UD
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