NEC PD703114 User Manual page 321

(3) Interrupt signal output upon compare match
An interrupt signal is output when the count value of TM10 matches the set value of the CM100, CM101,
Note Note
CC100 , or CC101
Note When CC100 and CC101 are set to the compare register mode.
(CM101 with Operation Mode Set to General-Purpose Timer Mode and Count Clock Set to f
Internal match signal
Remark f : Base clock
CLK
An interrupt signal such as the one illustrated in Figure 9-62 is output at the next count clock following a
match of the TM10 count value and the set value of the corresponding compare register.
(4) TM1UBD0 flag (bit 0 of STATUS0 register) operation
In the UDC mode (CMD bit of TUM0 register = 1), the TM1UBD0 flag changes as follows during TM10
up/down count operation at every internal operation clock.
Count clock
TM1UBD0
CHAPTER 9 TIMER/COUNTER FUNCTION
register. The interrupt generation timing is as follows.
Figure 9-62. Interrupt Output upon Compare Match
f
CLK
Count clock
TM10 0007H 0008H
CM101
INTCM101
Figure 9-63. TM1UBD0 Flag Operation
TM10 0000H 0001H 0000H
User's Manual U15195EJ5V0UD
0009H 000AH 000BH
0009H
0001H 0000H 0001H
/2)
CLK
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