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(2) Serial clock generation
A serial clock can be generated according to the settings of the CKSR0 and BRGC0 registers.
The base clock to the 8-bit counter is selected by the TPS3 to TPS0 bits of the CKSR0 register.
The 8-bit counter divisor value can be set by the MDL7 to MDL0 bits of the BRGC0 register.
(a) Clock select register 0 (CKSR0)
The CKSR0 register is an 8-bit register for selecting the base clock (f
The clock selected by the TPS3 to TPS0 bits becomes the base clock (f
reception module.
This register can be read or written in 8-bit units.
Cautions 1. The maximum allowable frequency of the base clock (f
2. Set the UARTCAE0 bit of the ASIM0 register to 0 before rewriting the TPS3 to TPS0
7
6
CKSR0
0
0
Bit position
Bit name
3 to 0
TPS3 to
TPS0
432
CHAPTER 10 SERIAL INTERFACE FUNCTION
when the system clock's frequency is 40 MHz, TPS3 to TPS0 bits cannot be set to
0000B.
At 40 MHz, set the TPS3 to TPS0 bits to a value other than 0000B, and set the
UARTCAE0 bit of the ASIM0 register to 1.
bits.
5
4
3
0
0
TPS3
Specifies the base clock (f
TPS3
TPS2
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
Remark f
: Internal system clock
XX
User's Manual U15195EJ5V0UD
2
1
0
TPS2
TPS1
TPS0
Function
)
CLK
TPS1
TPS0
0
0
f
XX
0
1
f
/2
XX
1
0
f
/4
XX
1
1
f
/8
XX
0
0
f
/16
XX
0
1
f
/32
XX
1
0
f
/64
XX
1
1
f
/128
XX
0
0
f
/256
XX
0
1
f
/512
XX
1
0
f
/1,024
XX
1
1
f
/2,048
XX
Arbitrary Arbitrary Setting prohibited
) using the TPS3 to TPS0 bits.
CLK
) of the transmission/
CLK
) is 20 MHz. Therefore,
CLK
Address
After reset
FFFFFA06H
00H
Base clock (f
)
CLK
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