NEC PD703114 User Manual page 232

CHAPTER 9 TIMER/COUNTER FUNCTION
[Operation]
In PWM mode 0, TM0n performs up/down count operation. When TM0n = 0000H during down counting, an
underflow interrupt (INTTM0n) is generated, and when TM0n = CM0n3 during up counting, a match interrupt
(INTCM0n3) is generated (n = 0, 1).
Switching from up counting to down counting is performed when TM0n and CM0n3 match (INTCM0n3), and
switching from down counting to up counting is performed when a TM0n underflow occurs after TM0n
becomes 0000H.
The PWM cycle in this mode is (BFCMn3 value × 2 × TM0n count clock). Note that the next PWM cycle width
is set to BFCMn3.
The data of BFCMn3 is automatically transferred by hardware to CM0n3 upon generation of the INTTM0n
interrupt. Furthermore, calculation is performed by software processing started by INTTM0n, and the data for
the next cycle is set to BFCMn3.
Data setting to CM0n0 to CM0n2, which control the PWM duty, is explained next.
Setting of data to CM0n0 to CM0n2 consists of setting the duty output from BFCMn0 to BFCMn2.
The values of BFCMn0 to BFCMn2 are automatically transferred by hardware to CM0n0 to CM0n2 upon
generation of the INTTM0n interrupt. Furthermore, software processing is started up and calculation
performed, and the set/reset timing of the F/F for the next cycle is set to BFCMn0 to BFCMn2.
The PWM cycle and the PWM duty are set in the above procedure.
The F/F set/reset conditions upon match of CM0n0 to CM0n2 are as follows.
• Set:
CM0n0 to CM0n2 match detection during TM0n up count operation
• Reset: CM0n0 to CM0n2 match detection during TM0n down count operation
In this mode, the F/F set/reset timing is performed at the same timing (right-left symmetric control). The
values of DTRRn are transferred to the corresponding dead-time timers (DTMn0 to DTMn2) in
synchronization with the set/reset timing of the F/F, and down counting is started. DTMn0 to DTMn2 count
down to 000H, and stop when they count down further to FFFH.
DTMn0 to DTMn2 can automatically generate a width at which the active levels of the positive phase (TO0n0,
TO0n2, TO0n4) and negative phase (TO0n1, TO0n3, TO0n5) do not overlap (dead time).
In this way, software processing is started by an interrupt (INTTM0n) that occurs once during every PWM
cycle after initial setting has been performed, and by setting the PWM cycle and PWM duty to be used in the
next cycle, it is possible to automatically output a PWM waveform to pins TO0n0 to TO0n5 taking into
consideration the dead-time width (in the case of an interrupt culling ratio of 1/1).
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User's Manual U15195EJ5V0UD