Time Required For Dma Transfer - NEC PD703114 User Manual

(2) Repetitively setting the INITn bit of the DCHCn register until the transfer is forcibly terminated
successfully
The preventive processing steps are shown below.
<1> Copy the initial transfer count of the channel to be forcibly terminated to a general-purpose register.
<2> Set the INITn bit of the DCHCn register of the channel to be forcibly terminated to 1.
<3> Read the value of DMA transfer count register n (DBCn) of the channel to be forcibly terminated and
compare it with the value copied in step <1>. If the values do not match, repeat steps <2> and <3>.
Cautions 1. When the DBCn register was read in step <3>, if DMA stops due to this restriction,
2. Note that this preventive method takes longer until the forcible termination in
Remark n = 0 to 3

6.13 Time Required for DMA Transfer

The overhead before and after DMA transfer and minimum execution clock for DMA transfer are shown below.
Table 6-3. Minimum Number of Execution Clocks in DMA Cycle
DMA Cycle
<1> Response time to DMA request
<2> Memory access Internal RAM access
On-chip peripheral I/O register access
Notes 1. If the external interrupt (INTPn) is specified as a start factor of DMA transfer, the time for noise elimination
is added to this value (n = 0 to 4, 100, 101, 20 to 25, 30, 31).
2. Two clocks are required for the DMA cycle.
The following shows the minimum number of execution clocks in a DMA cycle in each transfer mode.
Single transfer: DMA response time (<1>) + transfer source memory access (<2>) + 1
memory access (<2>)
Block transfer: DMA response time (<1>) + (transfer source memory access (<2>) + 1
memory access (<2>)) × number of transfers
Note One clock is inserted between the read and write cycles of any DMA transfer.
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
the remaining number of the transfer count is read. If the forcible termination is
successful, the initial transfer count is read.
applications in which DMA transfers of DMA channels other than those subject to
forcible termination are frequently performed.
User's Manual U15195EJ5V0UD
Minimum Number of Execution Clocks
Note 1
4 clocks
Note 2
2 clocks
4 clocks + number of waits by VSWC register
Note
+ transfer destination
Note
+ transfer destination
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