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Table 1-2. Differences Between V850E/IA1 and V850E/IA2 Register Setting Values
Register Name
System wait control register (VSWC)
Timer 1/timer 2 clock selection register
(PRM02)
Remark
For details, refer to the user's manual of each product.
1.2 Features
Number of instructions
Minimum instruction execution time
General-purpose registers
Instruction set
Memory space
External bus interface
Internal memory
Interrupts/exceptions
CHAPTER 1 INTRODUCTION
V850E/IA1
12H
00H or 01H
80
25 ns (@ internal 40 MHz operation)
32 bits × 32 registers
V850E1 (NB85E) CPU
Signed multiplication (32 bits × 32 bits → 64 bits): 1 or 2 clocks
Saturated operation instructions (with overflow/underflow detection function)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Long/short format load/store instructions
Signed load instructions
4 MB linear address space (shared by program and data)
Memory block division function: 2 MB/block
Programmable wait function
Idle state insertion function
16-bit data bus (address/data multiplexed)
16-/8-bit bus sizing function
External wait function
Part Number
µ
PD703114
µ
PD70F3114
External interrupts: 16 (including NMI)
Internal interrupts: 42 sources
Exceptions:
1 source
8 levels of priority can be specified
User's Manual U15195EJ5V0UD
V850E/IA2
02H
01H (initial value 00H)
Internal ROM
128 KB (mask ROM)
128 KB (flash memory)
Internal RAM
6 KB
6 KB
19
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