Bus Priority Order - NEC PD703114 User Manual

4.8 Bus Priority Order

There are three external bus cycles: DMA cycle, operand data access, and instruction fetch.
In order of priority, DMA cycle is the highest, followed by operand data access and instruction fetch, in that order.
An instruction fetch may be inserted between a read access and write access during a read modify write access.
Also, an instruction fetch may be inserted between bus accesses when the CPU bus is locked.
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CHAPTER 4 BUS CONTROL FUNCTION
Table 4-1. Bus Priority Order
Priority External Bus Cycle
Order
High DMA cycle
Operand data access
Low
Instruction fetch
User's Manual U15195EJ5V0UD
Bus Master
DMA controller
CPU
CPU