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(7) Timer input timing
(T
= –40 to +85°C, REGIN = 3.0 to 3.6 V, V
A
Parameter
TIUD10, TCUD10 high-/low-level
width
TIUD10, TCUD10 input time
difference
TCLRn high-/low-level width
TIm high-/low-level width
Note When setting the CESE1 and CESE0 bits of timer 2 count clock/control edge selection register 0 (CSE0) to 1
and 0, respectively.
Remarks 1. T: Digital filter sampling clock
T can be selected by setting the following registers.
• TIUD10, TCUD10, TCLR10:
Can be selected from f
timer 10 noise elimination time select register (NRC10).
• TCLR2, TI2:
Fixed to f
• TCLR3, TI3:
Can be selected from f
bits of the timer 3 noise elimination time selection register (NRC3) (f
timer 3 clock selection register (PRM03)).
2. f
: Internal system clock frequency
X
TIUD10 (input)
TCUD10 (input)
TCLRn (input)
TIm (input)
Remark
n = 10, 2, 3
m = 2, 3
652
CHAPTER 16 ELECTRICAL SPECIFICATIONS
= RV
DD
Symbol
t
,
<53>
WUDH
t
WUDL
t
<54>
PHUD
t
,
<55>
n = 10, 2 (other than for through input), 3
WTCH
t
WTCL
n = 2 (for through input
t
,
<56>
m = 2 (other than for through input), 3
WTIH
t
WTIL
m = 2 (for through input
/2, f
/4, f
XX
XX
XX
/2.
XX
/2, f
XXTM3
XXTM3
<53>
<54>
<53>
<55>
<56>
User's Manual U15195EJ5V0UD
= 5.0 V ±0.5 V, V
= V
DD
SS3
Conditions
Note
)
Note
)
/8, and f
/16 by setting the NRC101 and NRC100 bits of the
XX
/4, f
/8, and f
/16 by setting the NRC31 and NRC30
XXTM3
XXTM3
<54>
<53>
= CV
= 0 V, C
= 50 pF)
SS
SS
L
MIN.
MAX.
5T + 10
5T + 10
5T + 10
2T + 10
5T + 10
2T + 10
: Clock selected with the
XXTM3
<53>
<54>
<54>
<55>
<56>
Unit
ns
ns
ns
ns
ns
ns
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