Dma Trigger Factor Registers 0 To 3 (Dtfr0 To Dtfr3) - NEC PD703114 User Manual

6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)

These 8-bit registers are used to control the DMA transfer start trigger via interrupt requests from on-chip
peripheral I/O.
The interrupt requests set with these registers serve as DMA transfer start factors.
These registers can be read/written in 8-bit units. Only bit 7 (DFn) can be read/written in 1-bit units, and bits 5 to 0
(IFCn5 to IFCn0) can be read/written in 8-bit units. (n = 0 to 3).
Be sure to set bit 6 to 0. If it is set to 1, the operation is not guaranteed.
Cautions 1. Be sure to stop the DMA operation before making changes to DTFRn register settings.
2. Except INTP0 to INPT4 and INTP20 to INTP25 (when noise elimination by an analog filter is
selected), an interrupt request input in standby mode (IDLE or software STOP mode) does
not trigger DMA transfer.
3. INTCM004 and INTCM005 cannot be used as DMA trigger sources.
4. If the start factor for DMA transfer is changed using the IFCn5 to IFCn0 bits, be sure to clear
(0) the DFn bit with the instruction immediately after the change.
<7> 6
DF0 0
DTFR0
<7> 6
DF1 0
DTFR1
<7> 6
DF2 0
DTFR2
<7> 6
DF3 0
DTFR3
Bit position Bit name
7 DFn
Remark n = 0 to 3
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
5 4 3
IFC05 IFC04 IFC03
5 4 3
IFC15 IFC14 IFC13
5 4 3
IFC25 IFC24 IFC23
5 4 3
IFC35 IFC34 IFC33
This is a DMA transfer request flag.
Only 0 can be written to this bit.
0: No DMA transfer request
1: DMA transfer request
If the interrupt specified as the DMA transfer start factor occurs and it is necessary to clear
the DMA transfer request while DMA transfer is disabled (including when it is aborted by
NMI or forcibly stopped by software), stop the operation that has caused the interrupt (e.g.,
if serial reception is in progress, by disabling reception) and then clear the DFn bit.
If it is clearly known that the interrupt will not occur until the next DMA transfer is started, it
is not necessary to stop the operation that has caused the interrupt.
User's Manual U15195EJ5V0UD
2 1 0
IFC02 IFC01 IFC00
2 1 0
IFC12 IFC11 IFC10
2 1 0
IFC22 IFC21 IFC20
2 1 0
IFC32 IFC31 IFC30
Function
(1/3)
Address After reset
FFFFF810H 00H
Address After reset
FFFFF812H 00H
Address After reset
FFFFF814H 00H
Address After reset
FFFFF816H 00H
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