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6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3)
These 16-bit registers are used to control the DMA transfer modes for DMA channel n (n = 0 to 3). These registers
cannot be accessed during DMA operation.
They can be read/written in 16-bit units.
Be sure to set bits 13 to 8, 1, and 0 to 0. If they are set to 1, the operation is not guaranteed.
Cautions 1. The DS1 and DS0 bits are used to set how many bits of data are transferred.
When 8-bit data (DS1, DS0 bits = 00) is set, the lower data bus (AD0 to AD7) is not necessarily
used.
When the transfer data size is set to 16 bits, the transfer must start from an address with bit 1
of the lower address aligned to "0". In this case, the transfer cannot start from an odd
address.
2. Set the DADCn register when the corresponding channel is in one of the following periods
(the operation is not guaranteed if set at another timing).
• Time from system reset to the generation of the first DMA transfer
• Time from DMA transfer end (after terminal count) to the generation of the next DMA
transfer request
• Time from the forcible termination of DMA transfer (after the INITn bit of DMA channel
control register n (DCHCn) has been set to 1) to the generation of the next DMA transfer
request
15
14
13
DADC0
DS1
DS0
0
15
14
13
DADC1
DS1
DS0 0
15
14
13
DADC2
DS1
DS0 0
15
14
13
DADC3
DS1
DS0 0
Bit position
Bit name
15, 14
DS1, DS0
112
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
12
11
10
9
8
7
0
0
0
0
0
SAD1
SAD0
12
11
10
9
8
7
0
0
0
0
0 SAD1 SAD0 DAD1 DAD0 TM1 TM0
12
11
10
9
8
7
0
0
0
0
0 SAD1 SAD0 DAD1 DAD0 TM1 TM0
12
11
10
9
8
7
0
0
0
0
0 SAD1 SAD0 DAD1 DAD0 TM1 TM0
Sets the transfer data size for DMA transfer.
DS1
DS0
0
0
8 bits
0
1
16 bits
1
0
Setting prohibited
1
1
Setting prohibited
For the on-chip peripheral I/O registers, ensure the transfer size matches the access size.
User's Manual U15195EJ5V0UD
6
5
4
3
2
1
DAD1
DAD0
TM1
TM0
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Function
Transfer data size
0
Address
After reset
0
FFFFF0D0H
0000H
0
Address
After reset
0
FFFFF0D2H
0000H
0
Address
After reset
0
FFFFF0D4H
0000H
0
Address
After reset
0
FFFFF0D6H
0000H
(1/2)
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