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(c) Operation in UDC mode A
(i) Interval operation
The operations at the count clock following a match of the TM10 count value and the CM100 set
value are as follows.
• In case of up count operation: TM10 is cleared (0000H) and the INTCM100 interrupt is generated.
• In case of down count operation: The TM10 count value is decremented (−1) and the INTCM100
interrupt is generated.
Remark
The interval operation can be combined with the transfer operation.
(ii) Transfer operation
If TM10 becomes 0000H during down counting when the RLEN bit of the TMC10 register is 1, the
CM100 register set value is transferred to TM10 at the next count clock.
Remarks 1. Transfer enable/disable can be set using the RLEN bit of the TMC10 register.
2. The transfer operation can be combined with the interval operation.
Figure 9-57. Example of TM10 Operation When Interval Operation and Transfer Operation Are Combined
(iii) Compare function
TM10 connects two compare register (CM100, CM101) channels and two capture/compare register
(CC100, CC101) channels.
When the TM10 count value and the set value of one of the compare registers match, a match
interrupt (INTCM100, INTCM101, INTCC100
Note This match interrupt is generated when CC100 and CC101 are set to the compare register
mode.
(iv) Capture function
TM10 connects two capture/compare register (CC100, CC101) channels.
When CC100 and CC101 are set to the capture register mode, the value of TM10 is captured in
synchronization with the corresponding capture trigger signal.
INTCC101) is generated upon detection of the valid edge.
CHAPTER 9 TIMER/COUNTER FUNCTION
CM100 set value
TM10 count value
0000H
TM10 and CM100 match
& timer clear
Up count
User's Manual U15195EJ5V0UD
TM10 underflow
& CM100 data transfer
Down count
Note
Note
, INTCC101
) is output.
A capture interrupt (INTCC100,
317
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