NEC PD703114 User Manual page 245

[Output waveform width with respect to set value]
• PWM cycle = BFCMn3 × 2 × T
• Dead time width
T
Dnm
• Active width of positive phase (TO0n0, TO0n2, TO0n4 pins)
= { (CM0n3 − CM0nX
• Active width of negative phase (TO0n1, TO0n3, TO0n5 pins)
= (CM0nX + CM0nX
down
f : Base clock
CLK
T : TM0n count clock
TM0n
CM0nX : Set value of CM0n0 to CM0n2 while TM0n is counting up
up
CM0nX : Set value of CM0n0 to CM0n2 while TM0n is counting down
down
The pin level when the TO0n0 to TO0n5 pins are reset is high impedance state. When the control mode is
selected thereafter, the following levels are output until TM0n is started.
• TO0n0, TO0n2, TO0n4... When active low → High level
• TO0n1, TO0n3, TO0n5... When active low → Low level
The active level is set with the ALVTO bit of the TOMRn register. The default is active low.
Caution If a value such that the positive phase or negative phase active width is "0" or a negative
value is set in the above formula, the TO0n0 to TO0n5 pins output a waveform fixed to the
inactive level waveform with active width "0".
Remarks. 1 m = 0 to 2
n = 0, 1
2. The interrupt request signal occurrence conditions of INTCM010 to INTCM012, INTCM0n4,
and INTCM0n5 are shown below.
CM010 to CM012, CM0n4, CM0n5 ≤ CM0n3
CM010 to CM012, CM0n4, CM0n5 = 0000H
CM010 to CM012, CM0n4, CM0n5 > CM0n3
CHAPTER 9 TIMER/COUNTER FUNCTION
TM0n
= (DTRRn + 1)/f
CLK
) + (CM0n3 − CM0nX
up down
) × T − T
up TM0n Dnm
When active high → Low level
When active high → High level
Setting Condition
User's Manual U15195EJ5V0UD
) } × T − T
TM0n Dnm
INTCM010 to INTCM012, INTCM0n4,
INTCM0n5 Signal Occurrence Status
Occurs
Occurs
Does not occur
245