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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(2) Generation of exception in service program
Service program of maskable interrupt or exception
...
...
• EIPC saved to memory or register
• EIPSW saved to memory or register
...
• TRAP instruction
...
• Saved value restored to EIPSW
• Saved value restored to EIPC
• RETI instruction
The priority order for multiple interrupt servicing control has 8 levels, from 0 to 7 for each maskable interrupt
request (0 is the highest priority), but it can be set as desired via software. Setting of the priority order level is
done using the xxPRn0 to xxPRn2 bits of the interrupt control request register (xxlCn), which is provided for
each maskable interrupt request. After system reset, an interrupt request is masked by the xxMKn bit and the
priority order is set to level 7 by the xxPRn0 to xxPRn2 bits.
The priority order of maskable interrupts is as follows.
(High)
Level 0 > Level 1 > Level 2 > Level 3 > Level 4 > Level 5 > Level 6 > Level 7
Interrupt servicing that has been suspended as a result of multiple servicing control is resumed after the
servicing of the higher priority interrupt has been completed and the RETI instruction has been executed.
A pending interrupt request is acknowledged after the current interrupt servicing has been completed and the
RETI instruction has been executed.
Caution In a non-maskable interrupt servicing routine (time until the RETI instruction is executed),
maskable interrupts are suspended and not acknowledged.
← Exception such as TRAP instruction acknowledged.
User's Manual U15195EJ5V0UD
(Low)
171
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