NEC PD703114 User Manual page 350

Figure 9-69. Operation in Timer 2 Up/Down Count Mode (When TCRE0 Register's ECEEn bit = 0,
ECREn Bit = 0, CLREn Bit = 0, OSTEn Bit = 0, CEEn Bit = 1, CASE1 Bit = 0)
f
CLK
CT
Note 1
UDSEn1, UDSEn0 bits
ECLR
Note 2
R
CNT FFFEH
INTTM2n (output)
CNT = 0
Notes 1. UDSEn1, UDSEn0 bits of TCRE0 register
2. Can control TM20/TM21 clear by subchannel 0/5 compare match or count direction.
Remarks 1. f : Base clock
CLK
2. CNT: Count value of timer 2
CT: TM2n count signal input in 16-bit mode
ECLR: External control signal input from TCLR2 pin input
R: Compare match signal input (subchannel 0/5)
3. n = 0, 1
350
CHAPTER 9 TIMER/COUNTER FUNCTION
01B
Don't care
FFFFH 0000H 0001H
User's Manual U15195EJ5V0UD
0002H 0001H 0000H 0001H
10B
0002H 0003H 0002H