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(4) Clocked serial interface receive buffer registers L0, L1 (SIRBL0, SIRBL1)
The SIRBLn register is an 8-bit buffer register that stores receive data (n = 0, 1).
When the receive-only mode is set (TRMDn bit of CSIMn register = 0), the reception operation is started by
reading data from the SIRBLn register.
These registers are read-only, in 8-bit or 1-bit units.
In addition to reset input, these registers can also be initialized by clearing (0) the CSICAEn bit of the CSIMn
register.
The SIRBLn register is the same as the lower bytes of the SIRBn register.
Cautions 1. Read the SIRBLn register only when the 8-bit data length has been set (CCL bit of
CSIMn register = 0).
2. When the single transfer mode is set (AUTO bit of CSIMn register = 0), perform a read
operation only in the idle state (CSOTn bit of CSIMn register = 0). If the SIRBLn register
is read during data transfer, the data cannot be guaranteed.
7
6
SIRBL0
SIRB7
SIRB6
7
6
SIRBL1
SIRB7
SIRB6
Bit position
Bit name
7 to 0
SIRB7 to
SIRB0
CHAPTER 10 SERIAL INTERFACE FUNCTION
5
4
3
SIRB5
SIRB4
SIRB3
5
4
3
SIRB5
SIRB4
SIRB3
Stores receive data.
User's Manual U15195EJ5V0UD
2
1
0
SIRB2
SIRB1
SIRB0
2
1
0
SIRB2
SIRB1
SIRB0
Function
Address
After reset
FFFFF902H
00H
Address
After reset
FFFFF912H
00H
483
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