NEC PD703114 User Manual page 274

V850e/ia2 32-bit single-chip microcontrollers
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Figure 9-33. Change Timing from 100% Duty State (PWM Mode 2) (2/2)
(b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5)
TM0n
count value
0000H
BFCM0nx
CM0nx
Interrupt request
Remarks 1. n = 0, 1
2. x = 4, 5
3. b > CM0n3
4. INTCM0nx is generated on a match between TM0n and CM0nx (a and c in the above figure).
The timing at which the F/F is reset is upon occurrence of a match with CM0n0 to CM0n2 as usual.
274
CHAPTER 9 TIMER/COUNTER FUNCTION
CM0n3
a
CM0nx
match
a
b
b
a
b
INTCM0nx
INTCM0n3
User's Manual U15195EJ5V0UD
CM0n3
CM0n3
c
CM0nx
match
c
b
c
INTCM0n3
INTCM0n3
INTCM0nx INTCM0n3
CM0n3
d

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