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Notes 1.
dddddddd is the higher 8 bits of disp9.
2.
4 if there is an instruction to overwrite the contents of the PSW immediately before.
3.
If there is no wait state (3 + number of read access wait states)
4.
n is the total number of load registers in list12 (According to the number of wait states. If there are no
wait states, n is the total number of registers in list12. When n = 0, the operation is the same as n =
1.)
5.
RRRRR: Other than 00000
6.
Only the lower halfword of data is valid.
7.
ddddddddddddddddddddd is the higher 21 bits of disp22.
8.
ddddddddddddddd is the higher 15 bits of disp16.
9.
According to the number of wait states (1 if there are no wait states)
10. b: Bit 0 of disp16
11. According to the number of wait states (2 if there are no wait states)
12. In this instruction, although the source register is regarded as reg2 for convenience of the mnemonic
description, the reg1 field is used in the opcode. Therefore, the meanings of register specifications
assigned in the mnemonic description and in the opcode differ from those in other instructions.
rrrrr = regID specification
RRRRR = reg2 specification
13. iiiii: Lower 5 bits of imm9
IIII: Higher 4 bits of imm9
14. Shortened by 1 clock if reg2 = reg3 (lower 32 bits of result are not written to register) or reg3 = r0
(higher 32 bits of result are not written to register).
15. sp/imm: Specify in bits 19 and 20 of sub-opcode.
16. ff = 00: Load sp in ep.
01: Load sign-extended 16-bit immediate data (bits 47 to 32) in ep.
10: Load 16-bit immediate data (bits 47 to 32) logically shifted 16 bits to the right in ep.
11: Load 32-bit immediate data (bits 63 to 32) in ep.
17. n + 3 clocks when imm = imm32
18. rrrrr: Other then 00000
19. ddddddd is the higher 7 bits of disp8.
20. dddd is the higher 4 bits of disp5.
21. dddddd is the higher 6 bits of disp8.
22. In the MUL reg1, reg2, reg3 and MULU reg1, reg2, reg3 instructions, prevent a combination of
registers that satisfies all of the following conditions.
executed with the following conditions satisfied is not guaranteed.
• reg1 = reg3
• reg1 ≠ reg2
• reg1 ≠ r0
• reg3 ≠ r0
APPENDIX C INSTRUCTION SET LIST
User's Manual U15195EJ5V0UD
The operation when the instructions are
683
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