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7.3.7 Maskable interrupt status flag (ID)
The ID flag is bit 5 of the PSW and this controls the maskable interrupt's operating state, and stores control
information regarding enabling or disabling of interrupt requests.
31
PSW
0
0
0
0
Bit position
5
ID
7.3.8 Interrupt trigger mode selection
The valid edge of the INTPn, ADTRG0, ADTRG1, TIUD10, TCUD10, TCLR10, TCLR3, and TI3 pins can be
selected by program. The edge that can be selected as the valid edge is one of the following (n = 0 to 4, 20 to 25, 30,
31, 100, 101).
• Rising edge
• Falling edge
• Both the rising and falling edges
When the INTPn, ADTRG0, ADTRG1, TIUD10, TCUD10, TCLR10, TCLR3, and TI3 signals are edge-detected,
they become an interrupt source or capture trigger.
The valid edge is specified by external interrupt mode registers 1 and 2 (INTM1 and INTM2), signal edge selection
register 10 (SESA10), the valid edge selection register (SESC), and TM2 input filter mode registers 0 to 5 (FEM0 to
FEM5).
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
0
0
0
0
0
0
0
0
0
0
0
Bit name
Indicates whether maskable interrupt servicing is enabled or disabled.
0: Maskable interrupt request acknowledgment enabled
1: Maskable interrupt request acknowledgment disabled (pending)
This bit is set to 1 by the DI instruction and reset to 0 by the EI instruction. Its
value is also modified by the RETI instruction or LDSR instruction when
referencing the PSW.
Non-maskable interrupt requests and exceptions are acknowledged regardless of
this flag. When a maskable interrupt is acknowledged, the ID flag is
automatically set to 1 by hardware.
The interrupt request generated during the acknowledgment disabled period (ID
= 1) is acknowledged when the xxIFn bit of xxICn register is set to 1, and the ID
flag is reset to 0.
User's Manual U15195EJ5V0UD
8
7
6
5
0
0
0
0
0
0
0
0
0
NP
EP
ID
Function
4
3
2
1
0
After reset
SAT
CY
OV
S Z
00000020H
155
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