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(4) Operation of capture/compare register (subchannels 0, 5)
Figures 9-79 and 9-80 show the operation of the capture/compare register (subchannels 0, 5).
Figure 9-79. Capture Operation: Timer 2 Count Value Read Timing (When CMSE050 Register's
CCSEy Bit = 0, EEVEy Bit = 1, and CSCE0 Register's SEVEy Bit = 0)
f
CLK
CNT
0
Note 1
LNKEy
ED1
ED2
CAPTURE_S
READ_ENABLE_S
CVSEy0 register
Undefined
Notes 1.
LNKEy bit of CMSE050 register
2.
If an event occurs at this timing, it is ignored.
Remarks 1. f
: Base clock
CLK
2. CNT: Count value of timer 2
CAPTURE_S: Capture trigger signal of sub capture register
ED1, ED2: Capture event signal inputs from edge selector
READ_ENABLE_S: Read timing for CVSEy0 register
3. y = 0, 5
360
CHAPTER 9 TIMER/COUNTER FUNCTION
1
2
3
Note 2
User's Manual U15195EJ5V0UD
4
5
6
2
7
8
9
10
Note 2
6
9
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