NEC PD703114 User Manual page 286

(2) Interrupt generation timing
The interrupt generation timing at the TM0n count clock settings (PRM02 to PRM00 bits of the TMC0n
register) in the various modes is described below.
Figure 9-40. Interrupt Generation Timing in PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1
(Asymmetric Triangular Wave)
CM0nx
TM0n
0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H
f
CLK
INTCM0nx
INTTM0n
CM0nx
TM0n 0000H
f
CLK
INTCM0nx
INTTM0n
Cautions 1. INTCM0nx is generated at the next f
2. INTTM0n is generated at the next f
3. INTTM0n is generated at the next f
the count clock is 1/2, 1/8, 1/16, or 1/32.
Remarks 1. n = 0, 1
2. Where n = 0: x = 3 to 5
Where n = 1: x = 0 to 5
3. f : Base clock
CLK
286
CHAPTER 9 TIMER/COUNTER FUNCTION
(a) When count clock = f
0002H
(b) When count clock = f
0002H
0001H 0002H
after detection of a TM0n and CM0nx match.
CLK
after detection of a TM0n and 0000H match.
CLK
after detection of a TM0n and 0000H match, even if
CLK
User's Manual U15195EJ5V0UD
CLK
/4
CLK
0001H 0000H