Table of Contents
Advertisement
15
14
13
12
CSC0
CS33
CS32
CS31
CS30
15
14
13
12
CSC1
CS43
CS42
CS41
CS40
Bit position
Bit name
15 to 0
CSnm
(n = 0 to 7)
(m = 0 to 3)
Notes 1.
If both the CS0m and CS2m bits have been set to 0, if area 0 is accessed, CS1 will be output
regardless of the setting of the CS1m bit.
2.
When area 1 is accessed, CS3 will be output regardless of the setting of the CS3m bit.
3.
When area 2 is accessed, CS4 will be output regardless of the setting of the CS4m bit.
4.
If both the CS5m and CS7m bits have been set to 0, if area 3 is accessed, CS6 will be output
regardless of the setting of the CS6m bit.
Caution In the V850E/IA2, set the CS01 and CS00 bits to 11B so that CS0 is output to both block 0 and 1.
CHAPTER 4 BUS CONTROL FUNCTION
11
10
9
8
7
6
CS23
CS22
CS21
CS20
CS13
CS12
11
10
9
8
7
6
CS53
CS52
CS51
CS50
CS63
CS62
Chip select enabled by setting CSnm bit to 1.
CSnm
CS00
CS0 output during block 0 access
CS01
CS0 output during block 1 access.
CS02
CS0 output during block 2 access.
CS03
CS0 output during block 3 access.
CS10 to CS13
Note 1
CS20
CS2 output during block 0 access.
CS21
CS2 output during block 1 access.
CS22
CS2 output during block 2 access.
CS23
CS2 output during block 3 access.
CS30 to CS33
Note 2
CS40 to CS43
Note 3
CS50
CS5 output during block 7 access.
CS51
CS5 output during block 6 access.
CS52
CS5 output during block 5 access.
CS53
CS5 output during block 4 access.
CS60 to CS63
Note 4
CS70
CS7 output during block 7 access.
CS71
CS7 output during block 6 access.
CS72
CS7 output during block 5 access.
CS73
CS7 output during block 4 access.
User's Manual U15195EJ5V0UD
5
4
3
2
1
0
CS11
CS10
CS03
CS02
CS01
CS00
5
4
3
2
1
0
CS61
CS60
CS73
CS72
CS71
CS70
Function
CS operation
Address
After reset
FFFFF060H
2C11H
Address
After reset
FFFFF062H
2C11H
83
Advertisement
Table of Contents
