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Edition
2nd
Addition of Caution in 11.4 (1) A/D scan mode registers 00 and 10 (ADSCM00, ASDSCM10)
Change of description on bits that can be manipulated and change of explanation of FR2 to FR0
bits in 11.4 (2) A/D scan mode registers 01 and 11 (ADSCM01, ADSCM11)
Addition of 11.11.6 Timing that makes the A/D conversion result undefined
Addition of 11.12 How to Read A/D Converter Characteristics Table
Modification of description in 12.2 (1) Functions of each port
Modification of Figure 12-4 Type D Block Diagram
Modification of Figure 12-7 Type G Block Diagram
Modification of Figure 12-8 Type H Block Diagram
Modification of Figure 12-13 Type M Block Diagram
Addition of Figure 12-14 Type N Block Diagram
Change of description in 12.3.6 (1) Operation in control mode
Modification of Figure 12-15 Example of Noise Elimination Timing
Addition of Caution and change of description in 12.4.3 (1) Timer 2 input filter mode
registers 0 to 5 (FEM0 to FEM5)
Addition of 13.2 (2) <1> Reset circuit and <2> Reset timing
Addition of item and change of description in Table 13-2 Initial Values of CPU, Internal RAM,
and On-Chip Peripheral I/O After Reset
Modification of description in 14.1 Features
Addition and modification of description in 14.2 Functional Outline
Modification of Figure 14-1 Example of Connection When Using N-ch Transistor
Addition of Figure 14-2 Mount Pad Dimensions When Mounted on 2SD1950 (VL Standard
Product) (Glass Epoxy Board) (Unit: mm)
Addition of Figure 14-3 Connection When Using External Regulator
Addition and modification of description in Caution in 14.4 (1) Regulator control register
(REGC)
Addition of Caution in 15.2 Writing Using Flash Programmer
Addition of description in 15.2 (2) Off-board programming
Modification of description in 15.3 Programming Environment
Change of description in 15.4 (1) UART0
Change of description in 15.4 (2) CSI0
Change of description in 15.4 (3) Handshake-supported CSI communication
Modification of description in 15.5.8 Power supply
Change of description in B.2 Instruction Set (Alphabetical Order)
Addition of 100-pin plastic QFP (14 × 20) package
3rd
Addition of Table 1-2 Differences Between V850E/IA1 and V850E/IA2 Register Setting
Values
Modification of description in 4.2.1 Pin status during internal ROM, internal RAM, and on-
chip peripheral I/O access
Addition of Caution to 4.3.1 (1) Chip area select control registers 0, 1 (CSC0, CSC1)
Modification and deletion of description in 4.9.1 Program space
Addition of description to 6.3.1 (1) DMA source address registers 0H to 3H (DSA0H to
DSA3H)
Addition of description to 6.3.2 (1) DMA destination address registers 0H to 3H (DDA0H to
DDA3H)
APPENDIX D REVISION HISTORY
Major Revision up to Previous Edition
User's Manual U15195EJ5V0UD
(4/7)
Applied to:
CHAPTER 11 A/D
CONVERTER
CHAPTER 12
PORT FUNCTIONS
CHAPTER 13
RESET FUNCTION
CHAPTER 14
REGULATOR
CHAPTER 15
FLASH MEMORY
µ
(
PD70F3114)
APPENDIX B
INSTRUCTION SET
LIST
Throughout
CHAPTER 1
INTRODUCTION
CHAPTER 4 BUS
CONTROL
FUNCTION
CHAPTER 6 DMA
FUNCTIONS (DMA
CONTROLLER)
689
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