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(2) PWM mode 0: Triangular wave modulation (right-left symmetric waveform control)
[Setting procedure]
(a) Set PWM mode 0 (symmetric triangular wave) using the MOD01 and MOD00 bits of the TMC0n register.
Also set the active level of the TO0n0 to TO0n5 pins using the ALVTO bit of the TOMRn register (n = 0,
1).
(b) Set the count clock of TM0n using the PRM02 to PRM00 bits of the TMC0n register. The transfer
operation from BFCMn3 to CM0n3 is set using the BFTE3 bit, and the transfer operation from BFCMn0 to
BFCMn2, BFCMn4, and BFCMn5 to CM0n0 to CM0n2, CM0n4, and CM0n5 is set using the BFTEN bit.
(c) Set the initial values.
(i) Specify the interrupt culling ratio using the CUL02 to CUL00 bits of the TMC0n register.
(ii) Set the half-cycle width of the PWM cycle in BFCMn3.
• PWM cycle = BFCMn3 value × 2 × TM0n count clock
(The TM0n count clock is set by the TMC0n register.)
(iii) Set the dead-time width in DTRRn.
• Dead-time width = (DTRRn + 1)/f
f
: Base clock
CLK
(iv) Set the set/reset timing of the F/F used in the PWM cycle in BFCMn0 to BFCMn2.
(d) Clear (0) the TM0CEDn bit of the TMC0n register to enable dead-time timer operation. Set TM0CEDn =
1 when not using dead time.
(e) Setting (1) the TM0CEn bit of the TMC0n register starts TM0n counting, and a 6-channel PWM signal is
output from the TO0n0 to TO0n5 pins.
Cautions 1. Setting CM0n3 to 0000H is prohibited.
2. Setting BFCMnx > BFCMn3 is prohibited when the TM0CEn bit of the TMC0n register is
0 because the outputs of the TO0n0 to TO0n5 pins are the inverted levels of the settings
(x = 0 to 2). Also, setting BFCMnx > BFCMn3 is prohibited if the CM0nx register is 0
when the TM0CEn bit of the TMC0n register.
Remark
The TM0CEn bit of the TMC0n register indicates a transfer operation under the following
conditions.
• When TM0CEn bit of TMC0n register is 0
Transfer to the CM0n0 to CM0n2, CM0n4, and CM0n5 registers is performed at the next base
clock (f
CLK
• When TM0CEn bit of TMC0n register is 1
The value of the BFCMn0 to BFCMn2, BFCMn4, and BFCMn5 registers is transferred to the
CM0n0 to CM0n2, CM0n4, and CM0n5 registers upon occurrence of the INTTM0n interrupt.
Transfer enable/disable at this time is controlled by the BFTEN bit of the TMC0n register.
CHAPTER 9 TIMER/COUNTER FUNCTION
CLK
) after writing to the BFCMn0 to BFCMn2, BFCMn4, and BFCMn5 registers.
User's Manual U15195EJ5V0UD
231
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