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The V850E/IA2 is provided with an external bus interface function by which external I/O and memories, such as
ROM and RAM, can be connected.
4.1 Features
• 16-bit/8-bit data bus sizing function
• Wait function
• Programmable wait function: up to 7 wait states can be inserted
• External wait function via WAIT pin
• Idle state insertion function
• External device connection enabled via bus control/port alternate function pins
4.2 Bus Control Pins
The following pins are used for connection to external devices.
Bus Control Pin (Function When in Control Mode)
Address/data bus (AD0 to AD15)
Address bus (A16 to A21)
Read/write control (LWR/UWR, RD, ASTB)
External wait control (WAIT)
Internal system clock (CLKOUT)
Remark
In the case of ROMless mode, when the system is reset, each bus control pin becomes valid
unconditionally.
4.2.1 Pin status during internal ROM, internal RAM, and on-chip peripheral I/O access
When the internal ROM and RAM are accessed, both the address bus and address/data bus become undefined.
The external bus control signal becomes inactive.
When on-chip peripheral I/O are accessed, both the address bus and address/data bus output the address of the
on-chip peripheral I/O currently being accessed. No data is output. The external bus control signal becomes inactive.
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CHAPTER 4 BUS CONTROL FUNCTION
User's Manual U15195EJ5V0UD
Function When in Port Mode
PDL0 to PDL15 (port DL)
PDH0 to PDH5 (port DH)
PCT0, PCT1, PCT4, PCT6
(port CT)
PCM0 (port CM)
PCM1 (port CM)
Register for Port/Control
Mode Switching
PMCDL
PMCDH
PMCCT
PMCCM
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