Power Save Control; Overview - NEC PD703114 User Manual

8.5 Power Save Control

8.5.1 Overview

The power save function has the following three modes.
(1) HALT mode
In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the CPU's
operation clock stops.
continues, operation continues. The power consumption of the overall system can be reduced by intermittent
operation that is achieved due to a combination of HALT mode and normal operation mode.
The system is switched to HALT mode by a specific instruction (the HALT instruction).
(2) IDLE mode
In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the supply of
internal system clocks is stopped, which causes the overall system to stop.
When the system is released from IDLE mode, it can be switched to normal operation mode quickly because
the oscillator's oscillation stabilization time need not be secured.
The system is switched to IDLE mode according to a PSMR register setting.
IDLE mode is located midway between software STOP mode and HALT mode in relation to the clock
stabilization time and current consumption. It is used for situations in which a low current consumption mode
is to be used and the clock stabilization time is to be eliminated after the mode is released.
(3) Software STOP mode
In this mode, the overall system is stopped by stopping the clock generator (oscillator and PLL synthesizer).
The system enters an ultra-low power consumption state in which only leak current is lost.
The system is switched to software STOP mode according to a PSMR register setting.
(a) PLL mode
The system is switched to software STOP mode by setting the register by software.
synthesizer's clock output is stopped at the same time that the oscillator is stopped. After software STOP
mode is released, the oscillator's oscillation stabilization time must be secured while the system clock
stabilizes. Also, PLL lockup time may be required depending on the program. When a resonator or
external clock is connected, following the release of the software STOP mode, execution of the program
is started after the count time of the time base counter has elapsed.
(b) Direct mode
To stop the clock, set the X1 pin to low level. After the release of software STOP mode, execution of the
program is started after the count-time of the time base counter has elapsed.
CHAPTER 8 CLOCK GENERATION FUNCTION
Since the supply of clocks to on-chip peripheral functions other than the CPU
User's Manual U15195EJ5V0UD
The PLL
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