Transfer Target; Transfer Type And Transfer Target - NEC PD703114 User Manual

6.6 Transfer Target

6.6.1 Transfer type and transfer target

Table 6-1 lists the relationship between the transfer type and transfer target (√: Transfer enabled, ×: Transfer
disabled).
Table 6-1. Relationship Between Transfer Type and Transfer Target
On-chip peripheral I/O
External I/O
Internal RAM
External memory
Internal ROM
Note If the transfer target is the on-chip peripheral I/O, only the single transfer mode can be used.
Cautions 1. The operation is not guaranteed for combinations of transfer destination and source marked
with "×" in Table 6-1.
2. Addresses between 3FFF000H and 3FFFFFFH cannot be specified for the source and
destination address of DMA transfer. Be sure to specify an address between FFFF000H and
FFFFFFFH.
Remark If the target of the DMA transfer is an on-chip peripheral I/O register (transfer source/transfer
destination), be sure to specify the same transfer size as the register size. For example, in the case of
DMA transfer to an 8-bit register, be sure to specify byte (8-bit) transfer.
<16-bit transfer>
• Transfer from a 16-bit bus to an 8-bit bus
A read cycle (16 bits) is generated and then a write cycle (8 bits) is generated twice successively.
• Transfer from an 8-bit bus to a 16-bit bus
A read cycle (8 bits) is generated twice successively and then a write cycle (16 bits) is generated.
The data is written to the transfer target with the lower bits first then higher bits in little endian and
the higher bits then the lower bits in big endian.
<8-bit transfer>
• Transfer from a 16-bit bus to an 8-bit bus
A read cycle (the higher 8 bits go into a high-impedance state) is generated and then a write cycle (8
bits) is generated.
• Transfer from an 8-bit bus to a 16-bit bus
A read cycle (8 bits) is generated and then a write cycle (the higher 8 bits go into a high-impedance
state) is generated. The data is written to the transfer target with the lower bits first then higher bits
in little endian and the higher bits then the lower bits in big endian.
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
Internal ROM
×
Note
×
×
×
×
User's Manual U15195EJ5V0UD
Destination
On-Chip Internal RAM
Note
Peripheral I/O
√ √
√ √
√ ×
√ √
× ×
External Memory,
External I/O
√
√
√
√
×