NEC PD703114 User Manual page 678

C.2 Instruction Set (Alphabetical Order)
Mnemonic Operands
r r r r r 0 0 1 1 1 0 R R R R R GR[reg2] ← GR[reg2] + GR[reg1]
ADD reg1, reg2
r r r r r 0 1 0 0 1 0 i i i i i GR[reg2] ← GR[reg2] + sign-extend (imm5)
imm5, reg2
r r r r r 1 1 0 0 0 0 R R R R R GR[reg2] ← GR[reg1] + sign-extend (imm16)
ADDI imm16,
reg1, reg2
i i i i i i i i i i i i i i i i
r r r r r 0 0 1 0 1 0 R R R R R GR[reg2] ← GR[reg2] AND GR[reg1]
AND reg1, reg2
ANDI imm16, reg1, r r r r r 1 1 0 1 1 0 R R R R R
reg2
i i i i i i i i i i i i i i i i
Bcond disp9 d d d d d 1 0 1 1 d d d c c c c
BSH reg2, reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0
w w w w w 0 1 1 0 1 0 0 0 0 1 0
BSW reg2, reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0
w w w w w 0 1 1 0 1 0 0 0 0 0 0
0 0 0 0 0 0 1 0 0 0 i i i i i i CTPC ← PC + 2 (return PC)
CALLT imm6
CLR1 bit#3, 1 0 b b b 1 1 1 1 1 0 R R R R R
disp16[reg1]
d d d d d d d d d d d d d d d d
reg2, [reg1]
1 0 b b b 1 1 1 1 1 0 R R R R R
d d d d d d d d d d d d d d d d
CMOV cccc, imm5,
r r r r r 1 1 1 1 1 1 i i i i i
reg2, reg3
w w w w w 0 1 1 0 0 0 c c c c 0
cccc, reg1,
r r r r r 1 1 1 1 1 1 R R R R R
reg2, reg3
w w w w w 0 1 1 0 0 1 c c c c 0
r r r r r 0 0 1 1 1 1 R R R R R result ← GR[reg2] − GR[reg1]
CMP reg1, reg2
r r r r r 0 1 0 0 1 1 i i i i i result ← GR[reg2] − sign-extend (imm5)
imm5, reg2
CTRET
0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0
0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0
DBRET 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0
0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0
1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 DBPC ← PC + 2 (return PC)
DBTRAP
DI
0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0
0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0
678
APPENDIX C INSTRUCTION SET LIST
Opcode
GR[reg2] ← GR[reg1] AND zero-extend (imm 16)
if conditions are satisfied
then PC ← PC + sign extend
Note 1
(disp9)
GR[reg3] ← GR[reg2] (23:16) || GR[reg2] (31:24)||GR
[reg2] (7:0)||GR[reg2] (15:8)
GR[reg3] ← GR[reg2] (7:0) || GR[reg2] (15:8)||GR
[reg2] (23:16)||GR[reg2] (31:24)
CTPSW ← PSW
adr ← CTBP + zero-extend (imm6 logically shift left by 1)
PC ← CTBP + zero-extend (Load-memory (adr,
Halfword)
adr ← GR[reg1] + sign-extend (disp 16)
Z flag ← Not (Load-memory-bit (adr, bit#3))
Store-memory-bit (adr, bit#3, 0)
adr ← GR[reg1]
Z flag ← Not (Load-memory-bit (adr, reg2))
Store-memory-bit (adr, reg2, 0)
if conditions are satisfied
then GR[reg3] ← sign-extend (imm5)
else GR[reg3] ← GR[reg2]
if conditions are satisfied
then GR[reg3] ← GR[reg1]
else GR[reg3] ← GR[reg2]
PC ← CTPC
PSW ← CTPSW
PC ← DBPC
PSW ← DBPSW
DBPSW ← PSW
PSW.NP ← 1
PSW.EP ← 1
PSW.ID ← 1
PC ← 00000060H
PSW.ID ← 1
User's Manual U15195EJ5V0UD
Operation Execution Clock
i
1
1
1
1
1
3
Conditions satisfied
Note 2
Conditions not 1
satisfied
1
1
5
3
Note 3
3
Note 3
1
1
1
1
4
4
4
1
Flags
r I CY OV S Z
× × × ×
1 1
× × × ×
1 1
× × × ×
1 1
× ×
1 1 0
×
1 1 0 0
3 3
Note 2 Note 2
1 1
× × ×
1 1 0
× × ×
1 1 0
5 5
×
3 3
Note 3 Note 3
×
3 3
Note 3 Note 3
1 1
1 1
× × × ×
1 1
× × × ×
1 1
4 4 R R R R
4 4 R R R R
4 4
1 1
(1/5)
SAT
R
R