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CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
Figure 5-1. SRAM, External ROM, External I/O Access Timing (2/4)
(b) When reading (0 waits, address setup waits, address hold wait states inserted)
TASW
T1
TAHW
T2
T3
CLKOUT (output)
Address
A16 to A21 (output)
AD0 to AD15 (I/O)
Address
Data
ASTB (output)
RD (output)
H
UWR, LWR (output)
WAIT (input)
Remarks 1. The circles indicate the sampling timing.
2. Broken lines indicate high impedance.
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User's Manual U15195EJ5V0UD
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