NEC PD703114 User Manual page 185

(3) Power save control register (PSC)
This is an 8-bit register that controls the power save function.
If releasing of interrupts are enabled by the setting of the NMIM and INTM bits, the software STOP mode can
be released by an interrupt request (except when interrupt servicing is disabled by the interrupt mask
registers (IMR0 to IMR3)).
The software STOP mode is specified by the setting of the STB bit.
This register, which is one of the specific registers, is effective only when accessed by a specific sequence
during a write operation (see 3.4.9 Specific registers).
This register can be read or written in 8-bit or 1-bit units.
Be sure to clear bits 7 and 6 to 0. If they are set to 1, the operation is not guaranteed.
Caution It is impossible to set the STB bit and NMIM or INTM bit at the same time. Be sure to set the
STB bit after setting the NMIM or INTM bit.
7 6
PSC 0 0
Bit position Bit name
5 NMIM
4 INTM
1 STB
Note Setting these bits is valid only in the IDLE/software STOP mode.
Data is set in the power save control register (PSC) according to the following sequence.
<1> Set the power save mode register (PSMR) (with the following instructions).
• Store instruction (ST/SST instruction)
• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
<2> Prepare data in any one of the general-purpose registers to set to the specific register.
<3> Write arbitrary data to the command register (PRCMD).
<4> Set the power save control register (PSC) (with the following instructions).
• Store instruction (ST/SST instruction)
• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
<5> Assert the NOP instructions (5 instructions (<5> to <9>).
CHAPTER 8 CLOCK GENERATION FUNCTION
<5> <4> 3
NMIM INTM 0
This is the enable/disable setting bit for standby mode release using valid edge
Note
input of NMI .
0: Enables NMI cancellation
1: Disables NMI cancellation
This is the enable/disable setting for standby mode release using an unmasked
maskable interrupt (INTPn) (n = 0 to 4, 20 to 25, 30, 31, 100, 101)
0: Enables maskable interrupt cancellation
1: Disables maskable interrupt cancellation
Indicates the standby mode status.
If 1 is written to this bit, the system enters standby mode (when it is in IDLE or
software STOP mode). When standby mode is released, this bit is automatically
reset to 0.
0: Standby mode is released
1: Standby mode is in effect
User's Manual U15195EJ5V0UD
2 <1> 0
0 STB 0 FFFFF1FEH
Function
Address After reset
00H
Note
.
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