NEC PD703114 User Manual page 435

(3) Baud rate setting example
Baud Rate
(bps)
300
600
1200
2400
4800
9600
19200
31250
38400
76800
153600
312500
625000
1250000
Caution The maximum allowable frequency of the base clock (f
Remarks f : Internal system clock frequency
XX
f : Base clock frequency
CLK
k: Setting values of MDL7 to MDL0 bits in BRGC0 register
ERR: Baud rate error [%]
CHAPTER 10 SERIAL INTERFACE FUNCTION
Table 10-3. Baud Rate Generator Setting Data
f = 40 MHz
XX
f k ERR f
CLK CLK
10
f /2 65 0.16 f /2
XX XX
9
f /2 65 0.16 f /2
XX XX
8
f /2 65 0.16 f /2
XX XX
7
f /2 65 0.16 f /2
XX XX
6
f /2 65 0.16 f /2
XX XX
5
f /2 65 0.16 f /2
XX XX
4
f /2 65 0.16 f /2
XX XX
3
f /2 80 0 f /2
XX XX
3
f /2 65 0.16 f /2
XX XX
2
f /2 65 0.16 f /2
XX XX
1
f /2 65 0.16 f /2
XX XX
1
f /2 32 0 f /2
XX XX
1
f /2 16 0 f /2
XX XX
1
f /2 8 0 f /2
XX XX
User's Manual U15195EJ5V0UD
f = 33 MHz f
XX XX
k ERR f
CLK
8 7
215 –0.07 f /2
XX
7 6
215 –0.07 f /2
XX
6 5
215 –0.07 f /2
XX
5 4
215 –0.07 f /2
XX
4 3
215 –0.07 f /2
XX
3 2
215 –0.07 f /2
XX
2 1
215 –0.07 f /2
XX
2 1
132 0 f /2
XX
1 0
215 –0.07 f /2
XX
1 0
107 0.39 f /2
XX
1 0
54 –0.54 f /2
XX
1 0
26 1.54 f /2
XX
1 0
13 1.54 f /2
XX
−17.5 −
1
8
) is 20 MHz.
CLK
= 10 MHz
k ERR
130 0.16
130 0.16
130 0.16
130 0.16
130 0.16
130 0.16
130 0.16
80 0
130 0.16
65 0.16
33 –1.36
16 0
8 0
− −
435