Forcible Termination - NEC PD703114 User Manual

V850e/ia2 32-bit single-chip microcontrollers

Table of Contents

6.12 Forcible Termination

In addition to the forcible interruption operation by means of NMI input, DMA transfer can be forcibly terminated by

the INITn bit of the DCHCn register (n = 0 to 3).

An example of forcible termination by the INITn bit of the DCHCn register is illustrated below (n = 0 to 3).

Figure 6-9. Example of Forcible Termination of DMA Transfer

(a) Block transfer via DMA channel 3 is started during block transfer via DMA channel 2

DSA2, DDA2, DBC2,

DADC2, DCHC2

(internal signal)

(internal signal)

CPU CPU CPU CPU DMA2 DMA2 DMA2 DMA2 DMA2 CPU DMA3 DMA3 DMA3 DMA3 CPU CPU CPU

(b) When transfer is suspended during DMA channel 1 block transfer, and transfer under another

condition is executed

DSA1, DDA1, DBC1,

DADC1, DCHC1

(internal signal)

CPU CPU CPU CPU DMA1 DMA1 DMA1 DMA1 DMA1 DMA1 CPU CPU CPU CPU DMA1 DMA1 DMA1 CPU

The values of the DSAn, DDAn, and DBCn registers (n = 0 to 3) are retained even when DMA

transfer is forcibly terminated, because these registers are FIFO-format buffer registers. The next

transfer condition can be set to these registers even while DMA transfer is in progress. On the

other hand, the setting of the DADCn and DCHCn registers is invalid during DMA transfer because

these registers are not buffer registers (see 6.8 Next Address Setting Function, 6.3.4 DMA

addressing control registers 0 to 3 (DADC0 to DADC3), and 6.3.5 DMA channel control

registers 0 to 3 (DCHC0 to DCHC3)).

CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)

DSA3, DDA3, DBC3,

DADC3, DCHC3

User's Manual U15195EJ5V0UD

(INIT2 bit = 1)

DMA channel 3 transfer start

Forcible termination of DMA channel 2 transfer, bus released

(INIT1 bit = 1)

Forcible termination of DMA channel

1 transfer, bus released

DMA channel 3 terminal count

DMA channel 1

terminal count