NEC PD703114 User Manual page 238

Figure 9-17. Operation Timing in PWM Mode 0 (Symmetric Triangular Wave, BFCMnx ≥ CM0n3) (2/2)
(b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5)
count value
BFCMnx
Interrupt request
Remarks 1. n = 0, 1
2. x = 4, 5
3. INTCM0nx is generated on a match between TM0n and CM0nx (a in the above figure).
When a value greater than CM0n3 is set to BFCMn0 to BFCMn2, the positive phase side (TO0n0,
TO0n2, TO0n4 pins) outputs a low level, and the negative phase side (TO0n1, TO0n3, TO0n5 pins)
continues to output a high level. This feature is effective for outputting a low-level or high-level width
exceeding the PWM cycle in an application such as inverter control. Furthermore, if CM0n0 to CM0n2 =
CM0n3 is set, matching of TM0n and CM0n0 to CM0n2 is detected during down counting by TM0n, so
that the F/F remains reset as is, and is not set.
The above explanation applies to an active high case. In an active low case, the levels of positive and
negative phases are merely inverted and other operations remain the same.
238
CHAPTER 9 TIMER/COUNTER FUNCTION
CM0n3
a
TM0n
0000H
CM0nx CM0nx
match match
BFCMnx ≥ CM0n3
a
a
CM0nx
INTCM0n3
INTCM0nx INTCM0nx
User's Manual U15195EJ5V0UD
CM0n3
a
CM0nx match
(BFCMnx = CM0n3)
BFCMnx ≥ CM0n3
BFCMnx ≥ CM0n3
INTTM0n INTCM0n3
INTCM0nx
(BFCMnx = CM0n3)
INTTM0n