NEC PD703114 User Manual page 257

Figure 9-26. Change Timing from 100% Duty State (1) (PWM Mode 1) (1/2)
(a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2)
count value
BFCM0nx
CM0nx
Interrupt request
DTMnx
Positive phase
(TO0n0, TO0n2, TO0n4)
Negative phase
(TO0n1, TO0n3, TO0n5)
Note The F/F is reset upon INTTM0n occurrence.
Remarks 1. n = 0, 1
2. x = 0 to 2
3. t: Dead time = (DTRRn + 1)/f
4. The above figure shows an active-high case.
5. INTCM01x is generated on a match between TM01 and CM01x (a to d in the above figure).
INTCM00x is not generated.
CHAPTER 9 TIMER/COUNTER FUNCTION
CM0n3 CM0n3
a
b
TM0n
0000H
CM0nx CM0nx CM0nx
match match match
b 0000H 0000H 0000H 0000H
a b 0000H 0000H 0000H 0000H
INTCM0n3 INTTM0n INTCM0n3
INTCM01x INTCM01x
INTCM01x
F/F
t t
t
(f : Base clock)
CLK CLK
User's Manual U15195EJ5V0UD
CM0n3 CM0n3
c
CM0nx CM0nx
match match
c d
c
INTTM0n INTCM0n3 INTTM0n INTCM0n3
INTCM01x INTCM01x INTCM01x
Note
t
t
d
CM0nx
match
e
d e
INTTM0n
t
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