NEC PD703114 User Manual page 271

V850e/ia2 32-bit single-chip microcontrollers
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(a) When BFCMnx > CM0n3 is set
Figure 9-32. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx > CM0n3) (1/2)
(a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2)
count value
Interrupt request
Positive phase
(TO0n0, TO0n2, TO0n4)
Negative phase
(TO0n1, TO0n3, TO0n5)
Remarks 1. n = 0, 1
2. x = 0 to 2
3. b > CM0n3
4. t: Dead time = (DTRRn + 1)/f
5. The above figure shows an active-high case.
6. INTCM01x is generated on a match between TM01 and CM01x (a in the above figure).
INTCM00x is not generated.
CHAPTER 9 TIMER/COUNTER FUNCTION
a
TM0n
0000H
CM0nx
match
a
b
BFCMnx
a
CM0nx
INTCM01x
INTCM0n3
F/F
Set by rising edge of
TM0CEn bit
DTMnx
t
t
(f
: Base clock)
CLK
CLK
User's Manual U15195EJ5V0UD
CM0n3
CM0n3
b
b
INTCM0n3
t
CM0n3
b
b
INTCM0n3
271

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