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Figure 10-31. Repeat Transfer (Transmission/Reception) Timing Chart
SCKn (I/O)
SOn (output)
SIn (input)
SOTBFLn
dout-1
register
SOTBLn
dout-2
register
SIOLn
register
SIRBLn
register
SOTBFn (d1)
Reg_WR
SOTBn (d2)
Reg_RD
CSOTn bit
INTCSIn
interrupt
rq_clr
trans_rq
<1>
<3>
<2>
Remarks 1. n = 0, 1
2. Reg_WR: Internal signal. This signal indicates that the transmit data buffer register (SOTBn/
Reg_RD:
rq_clr: Internal signal. Transfer request clear signal.
trans_rq: Internal signal. Transfer request signal.
In the case of the repeat transfer mode, two transfer requests are set at the start of the first transfer.
Following the transmission/reception completion interrupt request (INTCSIn), transfer is continued if the
SOTBn register can be written within the next transfer reservation period. If the SOTBn register cannot
be written, transfer ends and the SIRBn register does not receive the new value of the SIOn register.
The last receive data can be obtained by reading the SIOn register following completion of the transfer.
502
CHAPTER 10 SERIAL INTERFACE FUNCTION
dout-1
dout-2
din-1
din-2
dout-3
din-1
SOTBn (d3)
SIRBn (d1)
<4>
<5>
<4>
<6>
Period during which
next transfer can be
reserved
SOTBLn) has been written.
Internal signal. This signal indicates that the receive data buffer register (SIRBn/
SIRBLn) has been read.
User's Manual U15195EJ5V0UD
dout-3
dout-4
din-3
din-4
dout-4
dout-5
din-2
din-3
SOTBn (d4)
SOTBn (d5)
SIRBn (d2)
SIRBn (d3)
<5>
<4>
<5>
dout-5
din-5
din-5
din-4
SIRBn (d4)
SIOn (d5)
<7>
<8>
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