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(2) Compare register 4 (CM4)
CM4 and the TM4 register count value are compared, and an interrupt request signal (INTCM4) is generated
when a match occurs. TM4 is cleared, synchronized with this match. If the TM4CAE0 bit of the TMC4
register is set to 0, a reset is performed asynchronously, and the registers are initialized.
The CM4 register has a master/slave configuration. When a write operation to a CM4 register is performed,
data is first written to the master register and then the master register data is transferred to the slave register.
In a compare operation, the slave register value is compared with the count value of the TM4 register. When
a read operation to the CM4 register is performed, data on the master side is read out.
CM4 can be read/written in 16-bit units.
Cautions 1. A write operation to the CM4 register requires 4 internal system clocks until the value
that was set in the CM4 register is transferred to internal units.
continuously to the CM4 register, be sure to reserve a time interval of at least 4 internal
system clocks.
2. The CM4 register can be overwritten only once in a single TM4 register cycle (from
0000H until an INTCM4 interrupt is generated due to a match of the TM4 register and
CM4 register). If this cannot be secured by the application, make sure that the CM4
register is not overwritten during timer operation.
3. Note that an INTCM4 interrupt will be generated after an overflow if a value less than the
counter value is written in the CM4 register during TM4 register operation (Figure 9-103).
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14 13 12
CM4
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CHAPTER 9 TIMER/COUNTER FUNCTION
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9
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User's Manual U15195EJ5V0UD
5
4
3
2
1
0
When writing
Address
After reset
FFFFF542H
0000H
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