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Figure 5-1. SRAM, External ROM, External I/O Access Timing (4/4)
CLKOUT (output)
A16 to A21 (output)
AD8 to AD15 (I/O)
AD0 to AD7 (I/O)
ASTB (output)
RD (output)
UWR, LWR (output)
WAIT (input)
Note AD0 to AD7 output invalid data when odd-numbered address byte data is accessed.
Remarks 1. The circles indicate the sampling timing.
2. Broken lines indicate high impedance.
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CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
(d) When writing (0 waits inserted, for 8-bit data bus)
T1
Address
H
User's Manual U15195EJ5V0UD
T2
T3
Address
Address
Note
Data
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