NEC PD703114 User Manual page 351

Figure 9-70. Timing in 32-Bit Cascade Operation Mode (When TCRE0 Register's UDSEn1,
UDSEn0 Bits = 00B, ECEEn Bit = 0, ECREn Bit = 0, CLREn Bit = 0, OSTEn Bit = 0,
CEEn Bit = 1, CASE1 Bit = 1)
f
CLK
CTC
Note
CASC [TB1]
CNT[TB0]
FFFBH
CNT[TB1]
Note If, in the 32-bit mode, CASC (CNT = MAX. for TM20) is input to TM21 and the CTC rising edge is
detected, TM21 performs a count operation.
Remarks 1. f : Base clock
CLK
2. CASC: TM21 count signal input in 32-bit mode
CNT: Count value of timer 2
CTC: TM21 count signal input in 32-bit mode
TB0: Count value of TM20
TB1: Count value of TM21
3. n = 0, 1
CHAPTER 9 TIMER/COUNTER FUNCTION
FFFCH FFFDH FFFEH
1234H
User's Manual U15195EJ5V0UD
FFFFH 0000H 0001H
1235H
0002H 0003H 0004H
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