NEC PD703114 User Manual page 466

V850e/ia2 32-bit single-chip microcontrollers
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Figure 10-23. Reception Completion Interrupt and Error Interrupt Generation Timing During
Receive data
Flag in reception
(SIR1)
Reception completion
interrupt
(INTSR1)
Error interrupt
Receive data
Flag in reception
(SIR1)
Reception completion
interrupt
(INTSR1)
Error interrupt
<Explanation>
(1) If the start bit of the second frame is not detected, no reception completion interrupt is generated.
(2) If an error occurs in the first frame, an error interrupt is generated following detection of the stop bit of
the first frame (at the calculated position).
(3) If an error occurs in the second frame, an error interrupt is generated simultaneously with a reception
completion interrupt.
If an error occurs in the first frame, no error interrupt is generated even if an error occurs in the
second frame.
466
CHAPTER 10 SERIAL INTERFACE FUNCTION
Synchronous Mode Reception
(a) During normal operation (in 1-frame reception mode)
START
(b) In 2-frame continuous reception mode
START
User's Manual U15195EJ5V0UD
STOP
START
(2)
STOP
STOP
(1)
(3)

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