NEC PD703114 User Manual page 496

Figure 10-28. Timing Chart According to Clock Phase Selection (2/2)
SCKn (I/O)
SIn (input)
SOn (output)
Reg_R/W
INTCSIn interrupt
CSOTn bit
SCKn (I/O)
SIn (input)
SOn (output)
Reg_R/W
INTCSIn interrupt
CSOTn bit
Remarks 1. n = 0, 1
2. Reg_R/W:
496
CHAPTER 10 SERIAL INTERFACE FUNCTION
(c) When CKP bit = 0, DAP bit = 1
DI7 DI6 DI5
DO7 DO6 DO5 DO4 DO3 DO2 DO1
(d) When CKP bit = 1, DAP bit = 1
DI7 DI6 DI5
DO7 DO6 DO5 DO4 DO3 DO2 DO1
Internal signal. This signal indicates that receive data buffer register (SIRBn/
SIRBLn) read or transmit data buffer register (SOTBn/SOTBLn) write was
performed.
User's Manual U15195EJ5V0UD
DI4 DI3 DI2 DI1 DI0
DO0
DI4 DI3 DI2 DI1 DI0
DO0